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RapidWright 2024.1.1-beta Release
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@clavin-xlnx clavin-xlnx released this 17 Jul 18:15
· 84 commits to master since this release
v2024.1.1-beta
c9f8c66
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GPG key ID: B5690EEEBB952194
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Release Notes:

  • [VivadoTools] Source *_load.tcl from same dir as DCP (#1032)
  • Test that PIP.isReversed() is correct (#1024)
  • Add TestSite.testGetIntTile() (#1022)
  • [EDIFTools] writeTclLoadScriptForPartialEncryptedDesigns abspath (#1029)
  • Adding HDIOB types (#1028)
  • Test for site routing from raw placed design (#1000)
  • [RWRoute] Do not NPE on encrypted netlists (#1025)
  • [RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM device (#1026)
  • Adds UNKWN state for LSFJobs (#1027)
  • Adding legacy support for u280 (#1021)
  • Remove flawed loop intended to for encrypted cell removal (#1023)
  • [DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus (#1009)
  • Fix null netlist pointer on expanded macro children (#1008)
  • [Interchange] Device Resources Verifier Fixes (#1014)
  • Fix ConcurrentModificationError (#1015)
  • [EDIFTools] Adding method to create a flat netlist from a hierarchical one (#1006)
  • Adding HBM ComponentTypes (#1007)
  • Test for wire/node mismatch reported in #983 (#1005)
  • 3.6% memory reduction usage for large placed designs (de-duplication of cell pin strings)
  • Add missing pin entry for BUFG_GT when tracking INT tile connections
  • Fixes rare DCP write issue with stubbed bi-directional PIPs (more common on DFX designs)
  • Fix for reversed flag on PIPs
  • Addresses issue with Net.getBufferDelay() by checking for null wire names
  • Fixes two site routing issues
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