Fixing 14b -> 13b

Xilinx · Sep 14, 2023 · 3e0dfec · 3e0dfec
1 parent 1789bee
commit 3e0dfec
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/src/brevitas_examples/super_resolution/README.md b/src/brevitas_examples/super_resolution/README.md
@@ -23,7 +23,7 @@ Note that this is a difference from many academic works that train only on the Y
 ||
 | [quant_espcn_x2_w4a4_base]()    | x2             | int4                | (u)int4                 | 30.30                  |
 | [quant_espcn_x2_w4a4_a2q_32b]() | x2             | int4                | (u)int4                 | 30.27                  |
-| [quant_espcn_x2_w4a4_a2q_14b]() | x2             | int4                | (u)int4                 | 30.24                  |
+| [quant_espcn_x2_w4a4_a2q_13b]() | x2             | int4                | (u)int4                 | 30.24                  |
 
 
 ## Train

diff --git a/src/brevitas_examples/super_resolution/models/__init__.py b/src/brevitas_examples/super_resolution/models/__init__.py
@@ -37,13 +37,13 @@
             weight_bit_width=4,
             act_bit_width=4,
             acc_bit_width=32),
-    'quant_espcn_x2_w4a4_a2q_14b':
+    'quant_espcn_x2_w4a4_a2q_13b':
         partial(
             quant_espcn_a2q,
             upscale_factor=2,
             weight_bit_width=4,
             act_bit_width=4,
-            acc_bit_width=14)}
+            acc_bit_width=13)}
 
 root_url = 'https://github.com/Xilinx/brevitas/releases/download/super_res-r0'