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Analytical FIFO sizing Pre-commit #1317: Pull request #1185 synchronize by lstasytis
October 15, 2024 16:10 43s lstasytis:feature/analytical-fifo-sizing
lstasytis:feature/analytical-fifo-sizing
October 15, 2024 16:10 43s
4-BIT DSP-MVU: Allow very wide lanes requiring even a high-lane extension. Pre-commit #1313: Pull request #1203 synchronize by preusser
October 15, 2024 15:19 44s tpreusse.mvu_harden
tpreusse.mvu_harden
October 15, 2024 15:19 44s
Pyxsi enablement for alternative rtl simulation Pre-commit #1312: Pull request #1213 synchronize by auphelia
October 14, 2024 12:50 32s feature/pyxsi_integration
feature/pyxsi_integration
October 14, 2024 12:50 32s
Merge pull request #1212 from Xilinx/hotfix/tutorial Pre-commit #1311: Commit ac2fa5a pushed by auphelia
October 11, 2024 15:59 35s dev
dev
October 11, 2024 15:59 35s
Pyxsi enablement for alternative rtl simulation Pre-commit #1310: Pull request #1213 synchronize by auphelia
October 11, 2024 15:59 33s feature/pyxsi_integration
feature/pyxsi_integration
October 11, 2024 15:59 33s
Pyxsi enablement for alternative rtl simulation Pre-commit #1309: Pull request #1213 synchronize by auphelia
October 11, 2024 09:54 32s feature/pyxsi_integration
feature/pyxsi_integration
October 11, 2024 09:54 32s
Pyxsi enablement for alternative rtl simulation Pre-commit #1308: Pull request #1213 synchronize by auphelia
October 11, 2024 09:53 28s feature/pyxsi_integration
feature/pyxsi_integration
October 11, 2024 09:53 28s
Pyxsi enablement for alternative rtl simulation Pre-commit #1307: Pull request #1213 synchronize by auphelia
October 11, 2024 09:49 37s feature/pyxsi_integration
feature/pyxsi_integration
October 11, 2024 09:49 37s
Pyxsi enablement for alternative rtl simulation Pre-commit #1306: Pull request #1213 opened by auphelia
October 11, 2024 09:45 38s feature/pyxsi_integration
feature/pyxsi_integration
October 11, 2024 09:45 38s
Update folding configuration for FPGA flow tutorial Pre-commit #1305: Pull request #1212 synchronize by auphelia
October 11, 2024 09:36 36s hotfix/tutorial
hotfix/tutorial
October 11, 2024 09:36 36s
Update folding configuration for FPGA flow tutorial Pre-commit #1304: Pull request #1212 opened by auphelia
October 11, 2024 08:48 35s hotfix/tutorial
hotfix/tutorial
October 11, 2024 08:48 35s
Merge pull request #1030 from iksnagreb/fix/round-and-clip-thresholds Pre-commit #1301: Commit 8da09eb pushed by auphelia
October 7, 2024 10:47 32s dev
dev
October 7, 2024 10:47 32s
4-BIT DSP-MVU: Allow very wide lanes requiring even a high-lane extension. Pre-commit #1300: Pull request #1203 opened by preusser
September 30, 2024 07:01 42s tpreusse.mvu_harden
tpreusse.mvu_harden
September 30, 2024 07:01 42s
Fix RoundAndClipThresholds Transformation Pre-commit #1299: Pull request #1030 synchronize by auphelia
September 27, 2024 14:36 36s iksnagreb:fix/round-and-clip-thresholds
iksnagreb:fix/round-and-clip-thresholds
September 27, 2024 14:36 36s
InsertDWC and multiple input/output nodes Pre-commit #1297: Pull request #1201 opened by mdanilow
September 26, 2024 16:05 43s mdanilow:fix/branched_dwc
mdanilow:fix/branched_dwc
September 26, 2024 16:05 43s
Merge pull request #1188 from mdanilow/fix/branched_structures Pre-commit #1296: Commit ab1c721 pushed by auphelia
September 26, 2024 16:04 38s dev
dev
September 26, 2024 16:04 38s
Fix RoundAndClipThresholds Transformation Pre-commit #1295: Pull request #1030 synchronize by auphelia
September 26, 2024 13:20 38s iksnagreb:fix/round-and-clip-thresholds
iksnagreb:fix/round-and-clip-thresholds
September 26, 2024 13:20 38s
Fix RoundAndClipThresholds Transformation Pre-commit #1294: Pull request #1030 synchronize by auphelia
September 26, 2024 11:57 30s iksnagreb:fix/round-and-clip-thresholds
iksnagreb:fix/round-and-clip-thresholds
September 26, 2024 11:57 30s
Fix RoundAndClipThresholds Transformation Pre-commit #1293: Pull request #1030 synchronize by auphelia
September 26, 2024 10:44 31s iksnagreb:fix/round-and-clip-thresholds
iksnagreb:fix/round-and-clip-thresholds
September 26, 2024 10:44 31s
Merge pull request #1198 from Xilinx/tpreusse.mvu_harden Pre-commit #1292: Commit 7076ed3 pushed by preusser
September 26, 2024 04:43 30s dev
dev
September 26, 2024 04:43 30s
Harden synthesis-time lane width computation against numeric overflow in exponentials. Pre-commit #1291: Pull request #1198 opened by preusser
September 25, 2024 12:34 37s tpreusse.mvu_harden
tpreusse.mvu_harden
September 25, 2024 12:34 37s
Different input datatypes support for AddStreams operation Pre-commit #1290: Pull request #1195 opened by mdanilow
September 23, 2024 13:47 37s mdanilow:feature/addstreams_inputdatatypes
mdanilow:feature/addstreams_inputdatatypes
September 23, 2024 13:47 37s
Fixes for branched structures Pre-commit #1284: Pull request #1188 synchronize by mdanilow
September 20, 2024 15:20 31s mdanilow:fix/branched_structures
mdanilow:fix/branched_structures
September 20, 2024 15:20 31s
Merge pull request #1192 from Xilinx/fix/preserve_onnx_dtype Pre-commit #1283: Commit 71b546b pushed by auphelia
September 19, 2024 14:29 3m 6s dev
dev
September 19, 2024 14:29 3m 6s
Preserve onnx tensor dtype when inserting FIFOs Pre-commit #1282: Pull request #1192 synchronize by auphelia
September 19, 2024 09:59 37s fix/preserve_onnx_dtype
fix/preserve_onnx_dtype
September 19, 2024 09:59 37s