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Pyxsi enablement for alternative rtl simulation #1213

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Pyxsi enablement for alternative rtl simulation #1213

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auphelia
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maltanar and others added 30 commits August 8, 2024 13:15
@maltanar
[Deps] add pyxsi fork and its deps
42cbf47
@maltanar
[Util] add util to fetch Vivado path
b6dba8a
@maltanar
[Sim] add a first draft of pyxsi-based simulation, untested
1468dbe
@maltanar
[Sim] try enabling pyxsi logging and tracing
6907167
@maltanar
[Op] experiment with enabling rtlsim with pyxsi
5a5461c
@maltanar
[Deps] update pyxsi
a50cdb6
@maltanar
[Sim] update pyxsi API to include verilog spec, assume precompiled
77680dd
@maltanar
[Deps] ensure pyxsi is compiled + set envvars for its use
1804c47
@maltanar
[Sim] remove LD_LIBRARY_PATH setting from pyxsi util, doesn't work
64e9fc1
@maltanar
[Deps] update pyxsi
d480e49
@maltanar
[AddStreams] set rtlsim_cycles for pyxsi prototyping
3560933
@maltanar
[Infra] only trigger pyxsi compile if Vivado detected
212927c
@maltanar
[Sim] move pyxsiutils to own repo, update deps, fix entrypoint chk
4fd5610
@maltanar
[pyxsi] trialling RPC server as LD_LIBRARY_PATH workaround
6e4d085
@maltanar
[Infra] remove global LD_LIBRARY_PATH setting from entrypoint
4558314
@maltanar
[pyxsi] add license text to rpcserver&client
aff109f
@maltanar
[Infra] start pyxsi rpc server in entrypoint
39ac22e
@maltanar
[Deps] update pyxsi
396cb8a
@maltanar
[Infra] redirect pyxsi rpcserver outputs to own logfile
948b5b3
@maltanar
[pyxsi] rework RPC interface to exclude rtlsim_multi_io
159e228
@maltanar
[Infra] don't launch pyxsi RPC server on startup (will be as needed)
6250c8f
@maltanar
[pyxsi] start (and then terminate when done) one pyxsi RPC server per…
42cbe0f 
… rtlsim
@auphelia
Merge branch 'dev' into feature/pyxsi_integration
db2d9a1
@maltanar @auphelia
[rtlsim] pyxsi for node-by-node rtlsim enablement via attribute
890ce81
@maltanar @auphelia
[Deps] update pyxsi
c04a4a8
@maltanar @auphelia
[pyxsi] expose close_rtlsim() to exit cleanly
b266a8a
@auphelia
[rtlsim] call close_rtlsim() to exit cleanly from pyxsi
ab3c36f
@maltanar @auphelia
[pyxsi] redirect rpcserver out to file for visible logging
fe7a942
@maltanar @auphelia
[HLS] use subcore path only if it exists
655b904
@maltanar @auphelia
[pyxsi] slightly more reliable start procedure for RPC server
acd88e5
alexhornburg-xlnx and others added 27 commits November 18, 2024 12:17
@alexhornburg-xlnx
[xsi] add Vivado lib path to global LD_LIBRARY_PATH again
04c34a0 
XSI needs to find some Vivado shared libraries. This can be done by adding it to  LD_LIBRARY_PATH.
However just adding this path by itself causes conflicts with libssl. It would pick up libssl within the Vivado installation instead of the system libssl. This causes various issues in using https, curl, wget or any kind of secure web download in the whole docker image.

The workaround to the above issue is to prepend the dockers system lib path (which contains libssl) before Vivados lib path in LD_LIBRARY_PATH.
@alexhornburg-xlnx
[xsi] replace pyxsi_rpc with pyxsi_utils
83dd944 
This commit removes the pyxsi RPC mechanism and instead calls pyxsi directly.
pyxsi depdency is updated to include a double free bugfix.
Ported pyxsi_utils from https://github.com/maltanar/pyxsi/tree/feature/utils
@auphelia @alexhornburg-xlnx
[pyxsi] Adjust copyright header and linting
d4bf3b3
@auphelia
Merge pull request #1225 from alexhornburg-xlnx/feature/pyxsi_link_poc
c0329e2 
Feature/pyxsi link poc
@auphelia
[Lint] Run pre-commit
bf1fafa
@auphelia
[pyxsi] Import optional to ensure non synthesis tests run
42582f9
@auphelia
[pyxsi] Enable both rtlsim backends in all HLS layers
63a7ef6
@maltanar @auphelia
[RTL] make it possible to use pyxsi as rtlsim backend
8812079
@maltanar @auphelia
[RTLMVU] prototyping support for pyxsi rtlsim
1115ddf
@maltanar @auphelia
[MVU] use rtlsim fxns from base class instead of pyverilator directly
28e482b
@auphelia
[pyxsi] Remove references to rpc setup in cherry-picked commits
6a16fdf
@auphelia
[pyxsi] Add support for pyxsi execution to rtl fmpadding, dwc, fifo
43b5437
@auphelia
[pyxsi] Enable pyxsi for rtl vvau
a44237b
@auphelia
[rtl thresh] Rename top module and fix intf names
c75678b
@preusser
Driving AXI bus padding to zero.
60fdd42
@auphelia
[pyxsi] Enable pyxsi for rtl swg
0a32c66
@auphelia
Merge branch 'dev' into feature/pyxsi_integration
e8e9ce3
@auphelia
Merge pull request #1234 from Xilinx/preusser.axi_pad_zero
24357f4 
Driving AXI bus padding to zero.
@auphelia
[SWG] Driving AXI bus padding to zero
563fbb1
@auphelia
[Tests] Default to pyxsi for testing
7dc169e
@maltanar @auphelia
[FIFO] default to xsi instead of pyverilator for FIFO depth setting
3b8d096
@maltanar
[Deps] update pyxsi
e45ffb5
@maltanar
[Test] use pyxsi for checksum test, including pre/post-hooks
af603f5
@maltanar
Merge branch 'feature/pyxsi_integration' of github.com:Xilinx/finn in…
9bbee05 
…to feature/pyxsi_integration
@maltanar
[Test] remove xfail from checksum test, works with pyxsi now
42b92c0
@auphelia
[Tests] Switch axilite read and write to pyxsi
3385927
@maltanar
[Test] convert negative ctrl reg vals to 2s complement in dynamic SWG…
68ce793 
… test
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@preusser preusser Awaiting requested review from preusser

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5 participants
@auphelia @maltanar @STFleming @alexhornburg-xlnx @preusser