Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Pyxsi enablement for alternative rtl simulation #1213

Draft
wants to merge 80 commits into
base: dev
Choose a base branch
from
Draft

Pyxsi enablement for alternative rtl simulation #1213

wants to merge 80 commits into from
+1,394 −620

Commits on Aug 8, 2024

  1. [Deps] add pyxsi fork and its deps

    @maltanar
    maltanar committed Aug 8, 2024
    Configuration menu
    Copy the full SHA
    42cbf47 View commit details
    Browse the repository at this point in the history

  2. [Util] add util to fetch Vivado path

    @maltanar
    maltanar committed Aug 8, 2024
    Configuration menu
    Copy the full SHA
    b6dba8a View commit details
    Browse the repository at this point in the history

  3. [Sim] add a first draft of pyxsi-based simulation, untested

    @maltanar
    maltanar committed Aug 8, 2024
    Configuration menu
    Copy the full SHA
    1468dbe View commit details
    Browse the repository at this point in the history

  4. [Sim] try enabling pyxsi logging and tracing

    @maltanar
    maltanar committed Aug 8, 2024
    Configuration menu
    Copy the full SHA
    6907167 View commit details
    Browse the repository at this point in the history

  5. [Op] experiment with enabling rtlsim with pyxsi

    @maltanar
    maltanar committed Aug 8, 2024
    Configuration menu
    Copy the full SHA
    5a5461c View commit details
    Browse the repository at this point in the history

Commits on Aug 14, 2024

  1. [Deps] update pyxsi

    @maltanar
    maltanar committed Aug 14, 2024
    Configuration menu
    Copy the full SHA
    a50cdb6 View commit details
    Browse the repository at this point in the history

  2. [Sim] update pyxsi API to include verilog spec, assume precompiled

    @maltanar
    maltanar committed Aug 14, 2024
    Configuration menu
    Copy the full SHA
    77680dd View commit details
    Browse the repository at this point in the history

Commits on Aug 19, 2024

  1. [Deps] ensure pyxsi is compiled + set envvars for its use

    @maltanar
    maltanar committed Aug 19, 2024
    Configuration menu
    Copy the full SHA
    1804c47 View commit details
    Browse the repository at this point in the history

  2. [Sim] remove LD_LIBRARY_PATH setting from pyxsi util, doesn't work

    @maltanar
    maltanar committed Aug 19, 2024
    Configuration menu
    Copy the full SHA
    64e9fc1 View commit details
    Browse the repository at this point in the history

Commits on Aug 20, 2024

  1. [Deps] update pyxsi

    @maltanar
    maltanar committed Aug 20, 2024
    Configuration menu
    Copy the full SHA
    d480e49 View commit details
    Browse the repository at this point in the history

  2. [AddStreams] set rtlsim_cycles for pyxsi prototyping

    @maltanar
    maltanar committed Aug 20, 2024
    Configuration menu
    Copy the full SHA
    3560933 View commit details
    Browse the repository at this point in the history

Commits on Aug 21, 2024

  1. [Infra] only trigger pyxsi compile if Vivado detected

    @maltanar
    maltanar committed Aug 21, 2024
    Configuration menu
    Copy the full SHA
    212927c View commit details
    Browse the repository at this point in the history

  2. [Sim] move pyxsiutils to own repo, update deps, fix entrypoint chk

    @maltanar
    maltanar committed Aug 21, 2024
    Configuration menu
    Copy the full SHA
    4fd5610 View commit details
    Browse the repository at this point in the history

Commits on Sep 9, 2024

  1. [pyxsi] trialling RPC server as LD_LIBRARY_PATH workaround

    @maltanar
    maltanar committed Sep 9, 2024
    Configuration menu
    Copy the full SHA
    6e4d085 View commit details
    Browse the repository at this point in the history

Commits on Oct 1, 2024

  1. [Infra] remove global LD_LIBRARY_PATH setting from entrypoint

    @maltanar
    maltanar committed Oct 1, 2024
    Configuration menu
    Copy the full SHA
    4558314 View commit details
    Browse the repository at this point in the history

  2. [pyxsi] add license text to rpcserver&client

    @maltanar
    maltanar committed Oct 1, 2024
    Configuration menu
    Copy the full SHA
    aff109f View commit details
    Browse the repository at this point in the history

Commits on Oct 3, 2024

  1. [Infra] start pyxsi rpc server in entrypoint

    @maltanar
    maltanar committed Oct 3, 2024
    Configuration menu
    Copy the full SHA
    39ac22e View commit details
    Browse the repository at this point in the history

  2. [Deps] update pyxsi

    @maltanar
    maltanar committed Oct 3, 2024
    Configuration menu
    Copy the full SHA
    396cb8a View commit details
    Browse the repository at this point in the history

  3. [Infra] redirect pyxsi rpcserver outputs to own logfile

    @maltanar
    maltanar committed Oct 3, 2024
    Configuration menu
    Copy the full SHA
    948b5b3 View commit details
    Browse the repository at this point in the history

  4. [pyxsi] rework RPC interface to exclude rtlsim_multi_io

    @maltanar
    maltanar committed Oct 3, 2024
    Configuration menu
    Copy the full SHA
    159e228 View commit details
    Browse the repository at this point in the history

Commits on Oct 4, 2024

  1. [Infra] don't launch pyxsi RPC server on startup (will be as needed)

    @maltanar
    maltanar committed Oct 4, 2024
    Configuration menu
    Copy the full SHA
    6250c8f View commit details
    Browse the repository at this point in the history

  2. [pyxsi] start (and then terminate when done) one pyxsi RPC server per… 

    … rtlsim
    @maltanar
    maltanar committed Oct 4, 2024
    Configuration menu
    Copy the full SHA
    42cbe0f View commit details
    Browse the repository at this point in the history

Commits on Oct 11, 2024

  1. Merge branch 'dev' into feature/pyxsi_integration

    @auphelia
    auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    db2d9a1 View commit details
    Browse the repository at this point in the history

  2. [rtlsim] pyxsi for node-by-node rtlsim enablement via attribute

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    890ce81 View commit details
    Browse the repository at this point in the history

  3. [Deps] update pyxsi

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    c04a4a8 View commit details
    Browse the repository at this point in the history

  4. [pyxsi] expose close_rtlsim() to exit cleanly

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    b266a8a View commit details
    Browse the repository at this point in the history

  5. [rtlsim] call close_rtlsim() to exit cleanly from pyxsi

    @auphelia
    auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    ab3c36f View commit details
    Browse the repository at this point in the history

  6. [pyxsi] redirect rpcserver out to file for visible logging

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    fe7a942 View commit details
    Browse the repository at this point in the history

  7. [HLS] use subcore path only if it exists

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    655b904 View commit details
    Browse the repository at this point in the history

  8. [pyxsi] slightly more reliable start procedure for RPC server

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    acd88e5 View commit details
    Browse the repository at this point in the history

  9. [prepare rtlsim] move rtlsim prep to rtlbackend for rtl layers

    @auphelia
    auphelia committed Oct 11, 2024
    Configuration menu
    Copy the full SHA
    c817adb View commit details
    Browse the repository at this point in the history

Commits on Oct 14, 2024

  1. [pyxsi] Make pyxsi import optional to allow GHA to work without insta… 

    …llation
    @auphelia
    auphelia committed Oct 14, 2024
    Configuration menu
    Copy the full SHA
    8d2daaf View commit details
    Browse the repository at this point in the history

Commits on Oct 15, 2024

  1. [PrepareRTLSim] Clean-up functions in rtl thresholding and move funct… 

    …ionality to rtlbackend
    @auphelia
    auphelia committed Oct 15, 2024
    Configuration menu
    Copy the full SHA
    1cc5f11 View commit details
    Browse the repository at this point in the history

Commits on Oct 17, 2024

  1. [rtlsim] enable stitched-IP rtlsim with pyxsi

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    20e8b59 View commit details
    Browse the repository at this point in the history

  2. [Deps] update pyxsi

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    cb6e08d View commit details
    Browse the repository at this point in the history

  3. [Deps] update pyxsi

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    7f09b73 View commit details
    Browse the repository at this point in the history

  4. Closing the handle if the simulation times out

    @STFleming @maltanar
    STFleming authored and maltanar committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    7018cfe View commit details
    Browse the repository at this point in the history

  5. [stitchedIP-rtlsim] Default rtlsim backend metadata prop to pyverilator

    @auphelia
    auphelia committed Oct 17, 2024
    Configuration menu
    Copy the full SHA
    812bde4 View commit details
    Browse the repository at this point in the history

Commits on Oct 22, 2024

  1. [prepare rtlsim] Clean-up functions in rtl mvu and vvu

    @auphelia
    auphelia committed Oct 22, 2024
    Configuration menu
    Copy the full SHA
    25443da View commit details
    Browse the repository at this point in the history

  2. [execute node] switch to rtlsim multi io for all custom ops

    @auphelia
    auphelia committed Oct 22, 2024
    Configuration menu
    Copy the full SHA
    afbf1fe View commit details
    Browse the repository at this point in the history

  3. [rtlsim] Delete obsolete rtlsim fct

    @auphelia
    auphelia committed Oct 22, 2024
    Configuration menu
    Copy the full SHA
    de5cf61 View commit details
    Browse the repository at this point in the history

  4. Merge branch 'dev' into feature/pyxsi_integration

    @auphelia
    auphelia committed Oct 22, 2024
    Configuration menu
    Copy the full SHA
    743644b View commit details
    Browse the repository at this point in the history

Commits on Oct 25, 2024

  1. [prepare rtlsim] Clean up new rtl op fcts

    @auphelia
    auphelia committed Oct 25, 2024
    Configuration menu
    Copy the full SHA
    2437687 View commit details
    Browse the repository at this point in the history

  2. [AddStreams] Enable both rtlsim backends

    @auphelia
    auphelia committed Oct 25, 2024
    Configuration menu
    Copy the full SHA
    cc30757 View commit details
    Browse the repository at this point in the history

Commits on Oct 29, 2024

  1. [xsi] add a firs C++ templatet draft for driving XSI rtlsim directly

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    e1a411b View commit details
    Browse the repository at this point in the history

  2. [xsi] remodel C++ driver from rtlsim_multi_io in pyxsi

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    600b999 View commit details
    Browse the repository at this point in the history

  3. [xsi] add comments to XSI C++ sim driver and Python fxn

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    2223fed View commit details
    Browse the repository at this point in the history

  4. [xsi] fix missing template, parse and return results dict

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    02f9c4b View commit details
    Browse the repository at this point in the history

  5. [xsi] util functions to read signals in C++ template

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    2ae55c1 View commit details
    Browse the repository at this point in the history

  6. [xsi] don't call prep_rtlsim_io_dict for dummy data

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    71a0964 View commit details
    Browse the repository at this point in the history

  7. [FIFO] introduce XSI-based FIFO sizing

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    9dba7c2 View commit details
    Browse the repository at this point in the history

  8. [xsi] make tracing optional

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    69df427 View commit details
    Browse the repository at this point in the history

  9. [FIFO] remove stitched IP and rtlsim metadata after FIFO sizing

    @maltanar @auphelia
    maltanar authored and auphelia committed Oct 29, 2024
    Configuration menu
    Copy the full SHA
    eab118d View commit details
    Browse the repository at this point in the history

Commits on Nov 18, 2024

  1. [xsi] add Vivado lib path to global LD_LIBRARY_PATH again 

    XSI needs to find some Vivado shared libraries. This can be done by adding it to  LD_LIBRARY_PATH.
However just adding this path by itself causes conflicts with libssl. It would pick up libssl within the Vivado installation instead of the system libssl. This causes various issues in using https, curl, wget or any kind of secure web download in the whole docker image.

The workaround to the above issue is to prepend the dockers system lib path (which contains libssl) before Vivados lib path in LD_LIBRARY_PATH.
    @alexhornburg-xlnx
    alexhornburg-xlnx committed Nov 18, 2024
    Configuration menu
    Copy the full SHA
    04c34a0 View commit details
    Browse the repository at this point in the history

  2. [xsi] replace pyxsi_rpc with pyxsi_utils 

    This commit removes the pyxsi RPC mechanism and instead calls pyxsi directly.
pyxsi depdency is updated to include a double free bugfix.
Ported pyxsi_utils from https://github.com/maltanar/pyxsi/tree/feature/utils
    @alexhornburg-xlnx
    alexhornburg-xlnx committed Nov 18, 2024
    Configuration menu
    Copy the full SHA
    83dd944 View commit details
    Browse the repository at this point in the history

  3. [pyxsi] Adjust copyright header and linting

    @auphelia @alexhornburg-xlnx
    auphelia authored and alexhornburg-xlnx committed Nov 18, 2024
    Configuration menu
    Copy the full SHA
    d4bf3b3 View commit details
    Browse the repository at this point in the history

Commits on Nov 19, 2024

  1. Merge pull request #1225 from alexhornburg-xlnx/feature/pyxsi_link_poc 

    Feature/pyxsi link poc
    @auphelia
    auphelia authored Nov 19, 2024
    Configuration menu
    Copy the full SHA
    c0329e2 View commit details
    Browse the repository at this point in the history

  2. [Lint] Run pre-commit

    @auphelia
    auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    bf1fafa View commit details
    Browse the repository at this point in the history

  3. [pyxsi] Import optional to ensure non synthesis tests run

    @auphelia
    auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    42582f9 View commit details
    Browse the repository at this point in the history

  4. [pyxsi] Enable both rtlsim backends in all HLS layers

    @auphelia
    auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    63a7ef6 View commit details
    Browse the repository at this point in the history

  5. [RTL] make it possible to use pyxsi as rtlsim backend

    @maltanar @auphelia
    maltanar authored and auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    8812079 View commit details
    Browse the repository at this point in the history

  6. [RTLMVU] prototyping support for pyxsi rtlsim

    @maltanar @auphelia
    maltanar authored and auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    1115ddf View commit details
    Browse the repository at this point in the history

  7. [MVU] use rtlsim fxns from base class instead of pyverilator directly

    @maltanar @auphelia
    maltanar authored and auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    28e482b View commit details
    Browse the repository at this point in the history

  8. [pyxsi] Remove references to rpc setup in cherry-picked commits

    @auphelia
    auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    6a16fdf View commit details
    Browse the repository at this point in the history

  9. [pyxsi] Add support for pyxsi execution to rtl fmpadding, dwc, fifo

    @auphelia
    auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    43b5437 View commit details
    Browse the repository at this point in the history

  10. [pyxsi] Enable pyxsi for rtl vvau

    @auphelia
    auphelia committed Nov 19, 2024
    Configuration menu
    Copy the full SHA
    a44237b View commit details
    Browse the repository at this point in the history

Commits on Nov 20, 2024

  1. [rtl thresh] Rename top module and fix intf names

    @auphelia
    auphelia committed Nov 20, 2024
    Configuration menu
    Copy the full SHA
    c75678b View commit details
    Browse the repository at this point in the history

Commits on Nov 22, 2024

  1. Driving AXI bus padding to zero.

    @preusser
    preusser committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    60fdd42 View commit details
    Browse the repository at this point in the history

  2. [pyxsi] Enable pyxsi for rtl swg

    @auphelia
    auphelia committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    0a32c66 View commit details
    Browse the repository at this point in the history

  3. Merge branch 'dev' into feature/pyxsi_integration

    @auphelia
    auphelia committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    e8e9ce3 View commit details
    Browse the repository at this point in the history

  4. Merge pull request #1234 from Xilinx/preusser.axi_pad_zero 

    Driving AXI bus padding to zero.
    @auphelia
    auphelia authored Nov 22, 2024
    Configuration menu
    Copy the full SHA
    24357f4 View commit details
    Browse the repository at this point in the history

  5. [SWG] Driving AXI bus padding to zero

    @auphelia
    auphelia committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    563fbb1 View commit details
    Browse the repository at this point in the history

  6. [Tests] Default to pyxsi for testing

    @auphelia
    auphelia committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    7dc169e View commit details
    Browse the repository at this point in the history

  7. [FIFO] default to xsi instead of pyverilator for FIFO depth setting

    @maltanar @auphelia
    maltanar authored and auphelia committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    3b8d096 View commit details
    Browse the repository at this point in the history

  8. [Deps] update pyxsi

    @maltanar
    maltanar committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    e45ffb5 View commit details
    Browse the repository at this point in the history

  9. [Test] use pyxsi for checksum test, including pre/post-hooks

    @maltanar
    maltanar committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    af603f5 View commit details
    Browse the repository at this point in the history

  10. Merge branch 'feature/pyxsi_integration' of github.com:Xilinx/finn in… 

    …to feature/pyxsi_integration
    @maltanar
    maltanar committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    9bbee05 View commit details
    Browse the repository at this point in the history

  11. [Test] remove xfail from checksum test, works with pyxsi now

    @maltanar
    maltanar committed Nov 22, 2024
    Configuration menu
    Copy the full SHA
    42b92c0 View commit details
    Browse the repository at this point in the history

Commits on Nov 25, 2024

  1. [Tests] Switch axilite read and write to pyxsi

    @auphelia
    auphelia committed Nov 25, 2024
    Configuration menu
    Copy the full SHA
    3385927 View commit details
    Browse the repository at this point in the history

Commits on Nov 26, 2024

  1. [Test] convert negative ctrl reg vals to 2s complement in dynamic SWG… 

    … test
    @maltanar
    maltanar committed Nov 26, 2024
    Configuration menu
    Copy the full SHA
    68ce793 View commit details
    Browse the repository at this point in the history