[stitchedIP-rtlsim] Default rtlsim backend metadata prop to pyverilator

notebooks/end2end_example/bnn-pynq/tfc_end2end_verification.ipynb

@@ -404,6 +404,7 @@
     "child_model = child_model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))\n",
     "child_model = child_model.transform(PrepareRTLSim())\n",
     "child_model.set_metadata_prop(\"exec_mode\",\"rtlsim\")\n",
+    "child_model.set_metadata_prop(\"rtlsim_backend\",\"pyverilator\")\n",
     "child_model.save(build_dir + \"/tfc_w1_a1_dataflow_child.onnx\");"
    ]
   },

src/finn/builder/build_dataflow_steps.py

@@ -250,6 +250,8 @@ def prepare_for_stitched_ip_rtlsim(verify_model, cfg):
     # set top-level prop for stitched-ip rtlsim and launch
     verify_model.set_metadata_prop("exec_mode", "rtlsim")
     # TODO make configurable
+    verify_model.set_metadata_prop("rtlsim_backend", "pyverilator")
+    # TODO make configurable
     # verify_model.set_metadata_prop("rtlsim_trace", "trace.vcd")
     return verify_model
 

src/finn/transformation/fpgadataflow/set_fifo_depths.py

@@ -324,6 +324,8 @@ def apply(self, model):
         model = model.transform(HLSSynthIP())
         model = model.transform(CreateStitchedIP(self.fpgapart, self.clk_ns))
         model.set_metadata_prop("exec_mode", "rtlsim")
+        # TODO: needs to check if pyxsi necessary
+        model.set_metadata_prop("rtlsim_backend", "pyverilator")
 
         if self.force_python_sim:
             # do rtlsim in Python for FIFO sizing

tests/end2end/test_end2end_bnn_pynq.py

@@ -746,6 +746,7 @@ def test_ipstitch_rtlsim(self, topology, wbits, abits, board):
         model = model.transform(HLSSynthIP())
         model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
         model.set_metadata_prop("exec_mode", "rtlsim")
+        model.set_metadata_prop("rtlsim_backend", "pyverilator")
         os.environ["LIVENESS_THRESHOLD"] = str(int(latency * 1.1))
         if rtlsim_trace:
             model.set_metadata_prop("rtlsim_trace", "%s_w%da%d.vcd" % (topology, wbits, abits))

tests/end2end/test_end2end_mobilenet_v1.py

@@ -502,6 +502,7 @@ def test_end2end_mobilenet_stitched_ip_rtlsim():
 
     # set top-level prop for stitched-ip rtlsim and launch
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     ret_rtlsim_ip = execute_onnx(model, inp_dict, True)
     res_rtlsim_ip = ret_rtlsim_ip[out_name]
     np.save(build_dir + "/end2end_mobilenet_result_rtlsim_ip.npy", res_rtlsim_ip)

tests/fpgadataflow/test_fpgadataflow_checksum.py

@@ -182,6 +182,7 @@ def test_fpgadataflow_checksum():
     model = model.transform(HLSSynthIP())
     model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
 
     # define function to read out the checksums from axilite
     checksums = []

tests/fpgadataflow/test_fpgadataflow_concat.py

@@ -157,6 +157,7 @@ def test_fpgadataflow_concat_stitchedip():
         )
     )
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     model.set_metadata_prop("rtlsim_trace", "trace.vcd")
     ret_sim = execute_onnx(model, inp_dict)
     assert (exp_out == ret_sim[oname]).all()

tests/fpgadataflow/test_fpgadataflow_convinputgenerator_rtl_dynamic.py

@@ -290,6 +290,7 @@ def test_fpgadataflow_conv_dynamic(cfg):
     model = model.transform(HLSSynthIP())
     model = model.transform(CreateStitchedIP("xc7z020clg400-1", 5, vitis=do_synth))
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
 
     # loop through experiment configurations
     for exp_cfg in exp_cfgs:
@@ -535,6 +536,7 @@ def test_fpgadataflow_slidingwindow_rtl_dynamic(
     model = model.transform(HLSSynthIP())
     model = model.transform(CreateStitchedIP("xc7z020clg400-1", 5))
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
 
     # Simulate 1 FM for each dimension in the series
     for i, ifm_dim in enumerate(ifm_dim_series):

tests/fpgadataflow/test_fpgadataflow_dwc.py

@@ -165,6 +165,7 @@ def test_fpgadataflow_dwc_stitched_rtlsim(config, impl_style):
     model = model.transform(HLSSynthIP())
     model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     y = oxe.execute_onnx(model, input_dict)["outp"]
 
     assert (

tests/fpgadataflow/test_fpgadataflow_ipstitch.py

@@ -272,6 +272,7 @@ def test_fpgadataflow_ipstitch_rtlsim(mem_mode):
     ]
     assert sorted(dir(sim.io)) == sorted(exp_io)
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     idt = model.get_tensor_datatype("inp")
     ishape = model.get_tensor_shape("inp")
     x = gen_finn_dt_tensor(idt, ishape)

tests/fpgadataflow/test_fpgadataflow_mvau.py

@@ -723,8 +723,8 @@ def test_fpgadataflow_rtl_mvau(mh, mw, pe, simd, idt, wdt, part, clk_ns):
     model = model.transform(HLSSynthIP())
     model = model.transform(CreateStitchedIP(part, clk_ns))
 
-    model.set_metadata_prop("rtlsim_so", "")
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     output_mvau_rtl_stitch = oxe.execute_onnx(model, input_dict)["global_out"]
 
     assert (

tests/fpgadataflow/test_fpgadataflow_thresholding_runtime.py

@@ -186,6 +186,7 @@ def test_runtime_thresholds_read(impl_style, idt_act_cfg, cfg, narrow, per_tenso
     model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model = model.transform(PrepareRTLSim())
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     # add two copies of the input tensor as the first one is just used to
     # "flush out" the pipeline (as mvau already starts receiving old weights while
     # we read/write new ones and reads seem to cause a disturbance too)
@@ -299,6 +300,7 @@ def test_runtime_thresholds_write(impl_style, idt_act_cfg, cfg, narrow, per_tens
     model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model = model.transform(PrepareRTLSim())
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     # add two copies of the input tensor as the first one is just used to
     # "flush out" the pipeline (as mvau already starts receiving old weights while
     # we read/write new ones and reads seem to cause a disturbance too)

tests/fpgadataflow/test_fpgadataflow_vvau.py

@@ -457,6 +457,7 @@ def test_fpgadataflow_vvau_rtl(kernel_size, in_feature_dim, in_chn, idt, wdt, pa
     partitioned_model = partitioned_model.transform(CreateStitchedIP(part, 5))
     # set top-level prop for stitched-ip rtlsim and launch
     partitioned_model.set_metadata_prop("exec_mode", "rtlsim")
+    partitioned_model.set_metadata_prop("rtlsim_backend", "pyverilator")
     # transpose input since we're now simulating HW layers (NCHW --> NHWC)
     input_dict["global_in"] = np.transpose(input_dict["global_in"], (0, 2, 3, 1))
     output_vvau_stitched = oxe.execute_onnx(

tests/fpgadataflow/test_runtime_weights.py

@@ -89,6 +89,7 @@ def test_runtime_weights_single_layer():
     model = model.transform(HLSSynthIP())
     model = model.transform(CreateStitchedIP(test_fpga_part, target_clk_ns))
     model.set_metadata_prop("exec_mode", "rtlsim")
+    model.set_metadata_prop("rtlsim_backend", "pyverilator")
     in_tensor = np.asarray(range(mw), dtype=np.float32)
     # add two copies of the input tensor as the first one is just used to
     # "flush out" the pipeline (as mvau already starts receiving old weights while