Fix format

Xilinx · Dec 12, 2024 · 45e07e7 · 45e07e7
1 parent ad9406e
commit 45e07e7
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Showing 2 changed files with 5 additions and 3 deletions.
diff --git a/llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp b/llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp
@@ -554,7 +554,7 @@ void NVPTXLowerArgs::handleByValParam(const NVPTXTargetMachine &TM,
 
   ArgUseChecker AUC(DL, IsGridConstant);
   ArgUseChecker::PtrInfo PI = AUC.visitArgPtr(*Arg);
-  bool ArgUseIsReadOnly  = !(PI.isEscaped() || PI.isAborted());
+  bool ArgUseIsReadOnly = !(PI.isEscaped() || PI.isAborted());
   // Easy case, accessing parameter directly is fine.
   if (ArgUseIsReadOnly && AUC.Conditionals.empty()) {
     // Convert all loads and intermediate operations to use parameter AS and

diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -29936,8 +29936,10 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
           SDValue Splat8 = DAG.getSplat(VT16, dl, Cst8);
           // Thie mask for the high bits is the same as the mask for the low
           // bits but shifted up by 8.
-          SDValue MaskHighBits = DAG.getNode(ISD::SHL, dl, VT16, MaskLowBits, Splat8);
-          SDValue Mask = DAG.getNode(ISD::OR, dl, VT16, MaskLowBits, MaskHighBits);
+          SDValue MaskHighBits =
+              DAG.getNode(ISD::SHL, dl, VT16, MaskLowBits, Splat8);
+          SDValue Mask =
+              DAG.getNode(ISD::OR, dl, VT16, MaskLowBits, MaskHighBits);
           // Finally, we mask the shifted vector with the SWAR mask.
           SDValue Masked = DAG.getNode(ISD::AND, dl, VT16, ShiftedR, Mask);
           return DAG.getBitcast(VT, Masked);