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Add verific verilog test cases for blackboxes
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mmicko committed Dec 6, 2024
1 parent 7d4aff6 commit 0539888
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17 changes: 17 additions & 0 deletions tests/verific/blackbox_empty.ys
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verific -sv <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
endmodule
EOF

verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF

verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL
41 changes: 41 additions & 0 deletions tests/verific/blackbox_ql.ys
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verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v

verific -sv <<EOF
module top (
input wire [19:0] a,
input wire [17:0] b,
output wire [37:0] z,
input wire clk,
input wire reset,
input wire unsigned_a,
input wire unsigned_b,
input wire f_mode,
input wire [2:0] output_select,
input wire register_inputs
);

// module instantiation
QL_DSP2_MULT_REGIN_REGOUT #(
.MODE_BITS(80'h1232324)
) u1 (
.a (a),
.b (b),
.z (z),
.clk (clk),
.reset (reset),

.unsigned_a (unsigned_a),
.unsigned_b (unsigned_b),

.f_mode (f_mode),
.output_select (output_select),
.register_inputs (register_inputs)
);
endmodule

EOF

verific -import top
hierarchy -top top
synth_quicklogic -family qlf_k6n10f
select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324

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