mem: only import attributes from ports if the memory doesn't have the…

…m yet
YosysHQ · Oct 30, 2023 · 2627631 · 2627631
1 parent 080da69
commit 2627631
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/kernel/mem.cc b/kernel/mem.cc
@@ -149,7 +149,8 @@ void Mem::emit() {
 				wr_port_xlat.push_back(i);
 		for (auto &port : rd_ports) {
 			for (auto attr: port.attributes)
-				cell->attributes.insert(attr);
+				if (!cell->has_attribute(attr.first))
+					cell->attributes.insert(attr);
 			if (port.cell) {
 				module->remove(port.cell);
 				port.cell = nullptr;
@@ -213,7 +214,8 @@ void Mem::emit() {
 		cell->setPort(ID::RD_DATA, rd_data);
 		for (auto &port : wr_ports) {
 			for (auto attr: port.attributes)
-				cell->attributes.insert(attr);
+				if (!cell->has_attribute(attr.first))
+					cell->attributes.insert(attr);
 			if (port.cell) {
 				module->remove(port.cell);
 				port.cell = nullptr;