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Merge pull request #4789 from YosysHQ/emil/sklansky-adder
Add a Sklansky option for `$lcu` mapping
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(* techmap_celltype = "$lcu" *) | ||
module _80_lcu_sklansky (P, G, CI, CO); | ||
parameter WIDTH = 2; | ||
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(* force_downto *) | ||
input [WIDTH-1:0] P, G; | ||
input CI; | ||
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(* force_downto *) | ||
output [WIDTH-1:0] CO; | ||
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integer i, j; | ||
(* force_downto *) | ||
reg [WIDTH-1:0] p, g; | ||
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast"; | ||
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always @* begin | ||
p = P; | ||
g = G; | ||
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// in almost all cases CI will be constant zero | ||
g[0] = g[0] | (p[0] & CI); | ||
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for (i = 0; i < $clog2(WIDTH); i = i + 1) begin | ||
// iterate in reverse so we don't confuse a result from this stage and the previous | ||
for (j = WIDTH - 1; j >= 0; j = j - 1) begin | ||
if (j & 2**i) begin | ||
g[j] = g[j] | p[j] & g[(j & ~(2**i - 1)) - 1]; | ||
p[j] = p[j] & p[(j & ~(2**i - 1)) - 1]; | ||
end | ||
end | ||
end | ||
end | ||
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assign CO = g; | ||
endmodule |
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yosys -import | ||
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read_verilog +/choices/sklansky.v | ||
read_verilog -icells lcu_refined.v | ||
design -save init | ||
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for {set i 1} {$i <= 16} {incr i} { | ||
design -load init | ||
chparam -set WIDTH $i | ||
yosys proc | ||
opt_clean | ||
equiv_make lcu _80_lcu_sklansky equiv | ||
equiv_simple equiv | ||
equiv_status -assert equiv | ||
} |