Merge branch 'master' into krys/docs

Fix failing verific tests

.gitignore

@@ -4,6 +4,7 @@
 *.gch
 *.gcda
 *.gcno
+*~
 __pycache__
 /.cproject
 /.project

CHANGELOG

@@ -2,9 +2,33 @@
 List of major changes and improvements between releases
 =======================================================
 
-Yosys 0.33 .. Yosys 0.34-dev
+Yosys 0.34 .. Yosys 0.35-dev
 --------------------------
 
+Yosys 0.33 .. Yosys 0.34
+--------------------------
+ * New commands and options
+    - Added option "-assert" to "sim" pass.
+    - Added option "-noinitstate" to "sim" pass.
+    - Added option "-dont_use" to "abc" pass.
+    - Added "dft_tag" pass to create tagging logic for data flow tracking.
+    - Added "future" pass to resolve future sampled value functions.
+    - Added "booth" pass to map $mul cells to Booth multipliers.
+    - Added option "-booth" to "synth" pass.
+
+ * SystemVerilog
+    - Added support for assignments within expressions, e.g., `x[y++] = z;` or
+      `x = (y *= 2) - 1;`.
+
+ * Verific support
+    - "src" attribute contain full location info.
+    - module parameters are kept after import.
+    - accurate access order semantics in memory inference.
+    - better "bind" support for mixed language projects.
+
+ * Various
+    - "show" command displays dot instead of box for wire aliases.
+
 Yosys 0.32 .. Yosys 0.33
 --------------------------
  * Various

Makefile

@@ -141,7 +141,7 @@ LDLIBS += -lrt
 endif
 endif
 
-YOSYS_VER := 0.33+34
+YOSYS_VER := 0.34+55
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -157,15 +157,15 @@ endif
 OBJS = kernel/version_$(GIT_REV).o
 
 bumpversion:
-	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 2584903.. | wc -l`/;" Makefile
+	sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 4a1b559.. | wc -l`/;" Makefile
 
 # set 'ABCREV = default' to use abc/ as it is
 #
 # Note: If you do ABC development, make sure that 'abc' in this directory
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = daad9ed
+ABCREV = 896e5e7
 ABCPULL = 1
 ABCURL ?= https://github.com/YosysHQ/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
@@ -357,7 +357,7 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := $(filter-out -lrt,$(LDLIBS))
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
+ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
 else ifeq ($(CONFIG),msys2-64)
@@ -368,7 +368,7 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := $(filter-out -lrt,$(LDLIBS))
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
+ABCMKARGS += LIBS="-lpthread -lshlwapi -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
 else ifneq ($(CONFIG),none)

README.md

@@ -592,6 +592,8 @@ from SystemVerilog:
 - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
   ports are inputs or outputs are supported.
 
+- Assignments within expressions are supported.
+
 
 Building the documentation
 ==========================

backends/cxxrtl/cxxrtl.h

@@ -1019,27 +1019,27 @@ struct metadata {
 
 	// In debug mode, using the wrong .as_*() function will assert.
 	// In release mode, using the wrong .as_*() function will safely return a default value.
-	const unsigned    uint_value = 0;
-	const signed      sint_value = 0;
+	const uint64_t    uint_value = 0;
+	const int64_t     sint_value = 0;
 	const std::string string_value = "";
 	const double      double_value = 0.0;
 
 	metadata() : value_type(MISSING) {}
-	metadata(unsigned value) : value_type(UINT), uint_value(value) {}
-	metadata(signed value) : value_type(SINT), sint_value(value) {}
+	metadata(uint64_t value) : value_type(UINT), uint_value(value) {}
+	metadata(int64_t value) : value_type(SINT), sint_value(value) {}
 	metadata(const std::string &value) : value_type(STRING), string_value(value) {}
 	metadata(const char *value) : value_type(STRING), string_value(value) {}
 	metadata(double value) : value_type(DOUBLE), double_value(value) {}
 
 	metadata(const metadata &) = default;
 	metadata &operator=(const metadata &) = delete;
 
-	unsigned as_uint() const {
+	uint64_t as_uint() const {
 		assert(value_type == UINT);
 		return uint_value;
 	}
 
-	signed as_sint() const {
+	int64_t as_sint() const {
 		assert(value_type == SINT);
 		return sint_value;
 	}
@@ -1068,6 +1068,9 @@ using debug_outline = ::_cxxrtl_outline;
 //
 // To avoid violating strict aliasing rules, this structure has to be a subclass of the one used
 // in the C API, or it would not be possible to cast between the pointers to these.
+//
+// The `attrs` member cannot be owned by this structure because a `cxxrtl_object` can be created
+// from external C code.
 struct debug_item : ::cxxrtl_object {
 	// Object types.
 	enum : uint32_t {
@@ -1103,6 +1106,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = item.data;
 		next    = item.data;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
@@ -1118,6 +1122,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.data);
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
@@ -1134,6 +1139,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = item.curr.data;
 		next    = item.next.data;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Width>
@@ -1149,6 +1155,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = item.data ? item.data[0].data : nullptr;
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
@@ -1164,6 +1171,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.data);
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
@@ -1180,6 +1188,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.curr.data);
 		next    = nullptr;
 		outline = nullptr;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits>
@@ -1195,6 +1204,7 @@ struct debug_item : ::cxxrtl_object {
 		curr    = const_cast<chunk_t*>(item.data);
 		next    = nullptr;
 		outline = &group;
+		attrs   = nullptr;
 	}
 
 	template<size_t Bits, class IntegerT>
@@ -1215,10 +1225,28 @@ struct debug_item : ::cxxrtl_object {
 };
 static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
 
+} // namespace cxxrtl
+
+typedef struct _cxxrtl_attr_set {
+	cxxrtl::metadata_map map;
+} *cxxrtl_attr_set;
+
+namespace cxxrtl {
+
+// Representation of an attribute set in the C++ interface.
+using debug_attrs = ::_cxxrtl_attr_set;
+
 struct debug_items {
 	std::map<std::string, std::vector<debug_item>> table;
-
-	void add(const std::string &name, debug_item &&item) {
+	std::map<std::string, std::unique_ptr<debug_attrs>> attrs_table;
+
+	void add(const std::string &name, debug_item &&item, metadata_map &&item_attrs = {}) {
+		std::unique_ptr<debug_attrs> &attrs = attrs_table[name];
+		if (attrs.get() == nullptr)
+			attrs = std::unique_ptr<debug_attrs>(new debug_attrs);
+		for (auto attr : item_attrs)
+			attrs->map.insert(attr);
+		item.attrs = attrs.get();
 		std::vector<debug_item> &parts = table[name];
 		parts.emplace_back(item);
 		std::sort(parts.begin(), parts.end(),
@@ -1246,6 +1274,10 @@ struct debug_items {
 	const debug_item &operator [](const std::string &name) const {
 		return at(name);
 	}
+
+	const metadata_map &attrs(const std::string &name) const {
+		return attrs_table.at(name)->map;
+	}
 };
 
 // Tag class to disambiguate the default constructor used by the toplevel module that calls reset(),

backends/cxxrtl/cxxrtl_backend.cc

@@ -2120,6 +2120,46 @@ struct CxxrtlWorker {
 		dec_indent();
 	}
 
+	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
+	{
+		if (metadata_map.empty()) {
+			f << "metadata_map()";
+			return;
+		}
+		f << "metadata_map({\n";
+		inc_indent();
+			for (auto metadata_item : metadata_map) {
+				if (!metadata_item.first.isPublic())
+					continue;
+				if (metadata_item.second.size() > 64 && (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) == 0) {
+					f << indent << "/* attribute " << metadata_item.first.str().substr(1) << " is over 64 bits wide */";
+					continue;
+				}
+				f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
+				// In Yosys, a real is a type of string.
+				if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
+					f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
+				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
+					f << escape_cxx_string(metadata_item.second.decode_string());
+				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED) {
+					f << "INT64_C(" << metadata_item.second.as_int(/*is_signed=*/true) << ")";
+				} else {
+					f << "UINT64_C(" << metadata_item.second.as_int(/*is_signed=*/false) << ")";
+				}
+				f << " },\n";
+			}
+		dec_indent();
+		f << indent << "})";
+	}
+
+	void dump_debug_attrs(const RTLIL::AttrObject *object)
+	{
+		dict<RTLIL::IdString, RTLIL::Const> attributes = object->attributes;
+		// Inherently necessary to get access to the object, so a waste of space to emit.
+		attributes.erase(ID::hdlname);
+		dump_metadata_map(attributes);
+	}
+
 	void dump_debug_info_method(RTLIL::Module *module)
 	{
 		size_t count_public_wires = 0;
@@ -2205,7 +2245,9 @@ struct CxxrtlWorker {
 							}
 							f << "debug_item::" << flag;
 						}
-						f << "));\n";
+						f << "), ";
+						dump_debug_attrs(wire);
+						f << ");\n";
 						count_member_wires++;
 						break;
 					}
@@ -2220,7 +2262,9 @@ struct CxxrtlWorker {
 							f << "debug_eval_outline";
 						else
 							f << "debug_alias()";
-						f << ", " << mangle(aliasee) << ", " << wire->start_offset << "));\n";
+						f << ", " << mangle(aliasee) << ", " << wire->start_offset << "), ";
+						dump_debug_attrs(aliasee);
+						f << ");\n";
 						count_alias_wires++;
 						break;
 					}
@@ -2230,14 +2274,18 @@ struct CxxrtlWorker {
 						dump_const(debug_wire_type.sig_subst.as_const());
 						f << ";\n";
 						f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
-						f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "));\n";
+						f << ", debug_item(const_" << mangle(wire) << ", " << wire->start_offset << "), ";
+						dump_debug_attrs(wire);
+						f << ");\n";
 						count_const_wires++;
 						break;
 					}
 					case WireType::OUTLINE: {
 						// Localized or inlined, but rematerializable wire
 						f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
-						f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "));\n";
+						f << ", debug_item(debug_eval_outline, " << mangle(wire) << ", " << wire->start_offset << "), ";
+						dump_debug_attrs(wire);
+						f << ");\n";
 						count_inline_wires++;
 						break;
 					}
@@ -2254,7 +2302,13 @@ struct CxxrtlWorker {
 						continue;
 					f << indent << "items.add(path + " << escape_cxx_string(mem.packed ? get_hdl_name(mem.cell) : get_hdl_name(mem.mem));
 					f << ", debug_item(" << mangle(&mem) << ", ";
-					f << mem.start_offset << "));\n";
+					f << mem.start_offset << "), ";
+					if (mem.packed) {
+						dump_debug_attrs(mem.cell);
+					} else {
+						dump_debug_attrs(mem.mem);
+					}
+					f << ");\n";
 				}
 				for (auto cell : module->cells()) {
 					if (is_internal_cell(cell->type))
@@ -2282,33 +2336,6 @@ struct CxxrtlWorker {
 		}
 	}
 
-	void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
-	{
-		if (metadata_map.empty()) {
-			f << "metadata_map()";
-			return;
-		}
-		f << "metadata_map({\n";
-		inc_indent();
-			for (auto metadata_item : metadata_map) {
-				if (!metadata_item.first.begins_with("\\"))
-					continue;
-				f << indent << "{ " << escape_cxx_string(metadata_item.first.str().substr(1)) << ", ";
-				if (metadata_item.second.flags & RTLIL::CONST_FLAG_REAL) {
-					f << std::showpoint << std::stod(metadata_item.second.decode_string()) << std::noshowpoint;
-				} else if (metadata_item.second.flags & RTLIL::CONST_FLAG_STRING) {
-					f << escape_cxx_string(metadata_item.second.decode_string());
-				} else {
-					f << metadata_item.second.as_int(/*is_signed=*/metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED);
-					if (!(metadata_item.second.flags & RTLIL::CONST_FLAG_SIGNED))
-						f << "u";
-				}
-				f << " },\n";
-			}
-		dec_indent();
-		f << indent << "})";
-	}
-
 	void dump_module_intf(RTLIL::Module *module)
 	{
 		dump_attrs(module);