verific: expose library name as module attribute

YosysHQ · Apr 15, 2024 · af94123 · af94123
1 parent 7bb2746
commit af94123
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
@@ -1430,6 +1430,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 	}
 	import_attributes(module->attributes, nl, nl);
 	module->set_string_attribute(ID::hdlname, nl->CellBaseName());
+	module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
 #ifdef VERIFIC_VHDL_SUPPORT
 	if (nl->IsFromVhdl()) {
 		NameSpace name_space(0);