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Merge pull request #4779 from YosysHQ/emil/han-carlson-adder
Add a Han-Carlson option for `$lcu` mapping
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(* techmap_celltype = "$lcu" *) | ||
module _80_lcu_han_carlson (P, G, CI, CO); | ||
parameter WIDTH = 2; | ||
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(* force_downto *) | ||
input [WIDTH-1:0] P, G; | ||
input CI; | ||
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(* force_downto *) | ||
output [WIDTH-1:0] CO; | ||
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integer i, j; | ||
(* force_downto *) | ||
reg [WIDTH-1:0] p, g; | ||
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always @* begin | ||
i = 0; | ||
p = P; | ||
g = G; | ||
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// in almost all cases CI will be constant zero | ||
g[0] = g[0] | (p[0] & CI); | ||
if (i < $clog2(WIDTH)) begin | ||
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// First layer: BK | ||
for (j = WIDTH - 1; j >= 0; j = j - 1) begin | ||
if (j % 2 == 1) begin | ||
g[j] = g[j] | p[j] & g[j - 1]; | ||
p[j] = p[j] & p[j - 1]; | ||
end | ||
end | ||
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// Inner (log(WIDTH) - 1) layers: KS | ||
for (i = 1; i < $clog2(WIDTH); i = i + 1) begin | ||
for (j = WIDTH - 1; j >= 2**i; j = j - 1) begin | ||
if (j % 2 == 1) begin | ||
g[j] = g[j] | p[j] & g[j - 2**i]; | ||
p[j] = p[j] & p[j - 2**i]; | ||
end | ||
end | ||
end | ||
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// Last layer: BK | ||
if (i < ($clog2(WIDTH) + 1)) begin | ||
for (j = WIDTH - 1; j >= 0; j = j - 1) begin | ||
if ((j % 2 == 0) && (j > 0)) begin | ||
g[j] = g[j] | p[j] & g[j - 1]; | ||
p[j] = p[j] & p[j - 1]; | ||
end | ||
end | ||
end | ||
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end | ||
end | ||
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assign CO = g; | ||
endmodule |
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yosys -import | ||
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read_verilog +/choices/han-carlson.v | ||
read_verilog -icells lcu_refined.v | ||
design -save init | ||
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for {set i 1} {$i <= 16} {incr i} { | ||
design -load init | ||
chparam -set WIDTH $i | ||
yosys proc | ||
opt_clean | ||
equiv_make lcu _80_lcu_han_carlson equiv | ||
equiv_simple equiv | ||
equiv_status -assert equiv | ||
} |
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yosys -import | ||
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read_verilog +/choices/kogge-stone.v | ||
read_verilog -icells lcu_refined.v | ||
design -save init | ||
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for {set i 1} {$i <= 16} {incr i} { | ||
design -load init | ||
chparam -set WIDTH $i | ||
yosys proc | ||
opt_clean | ||
equiv_make lcu _80_lcu_kogge_stone equiv | ||
equiv_simple equiv | ||
equiv_status -assert equiv | ||
} |
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module lcu (P, G, CI, CO); | ||
parameter WIDTH = 2; | ||
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input [WIDTH-1:0] P, G; | ||
input CI; | ||
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output [WIDTH-1:0] CO; | ||
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reg [WIDTH-1:0] p, g; | ||
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\$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO)); | ||
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endmodule |
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@@ -1,4 +1,4 @@ | ||
#!/usr/bin/env bash | ||
set -eu | ||
source ../gen-tests-makefile.sh | ||
run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'" | ||
run_tests --yosys-scripts --tcl-scripts --bash --yosys-args "-e 'select out of bounds'" |