intel_alm: convert to memory_libmap

techlibs/intel_alm/Makefile.inc

@@ -21,6 +21,7 @@ $(eval $(call add_share_file,share/intel_alm/cyclonev,techlibs/intel_alm/cyclone
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k.txt))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_m10k_map.v))
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
+$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab_map.v))
 
 # Miscellaneous
 $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))

techlibs/intel_alm/common/bram_m10k.txt

@@ -1,29 +1,16 @@
-bram $__MISTRAL_M10K
-    init   1
-    abits 13   @D8192x1
-    dbits  1   @D8192x1
-    abits 12   @D4096x2
-    dbits  2   @D4096x2
-    abits 11   @D2048x5
-    dbits  5   @D2048x5
-    abits 10   @D1024x10
-    dbits 10   @D1024x10
-    abits  9   @D512x20
-    dbits 20   @D512x20
-    abits  8   @D256x40
-    dbits 40   @D256x40
-    groups 2
-    ports  1 1
-    wrmode 1 0
-    # read enable; write enable + byte enables (only for multiples of 8)
-    enable 1 1
-    transp 0 0
-    clocks 1 1
-    clkpol 1 1
-endbram
-
-
-match $__MISTRAL_M10K
-    min efficiency 5
-    make_transp
-endmatch
+ram block $__MISTRAL_M10K {
+    abits 13;
+    widths 1 2 5 10 20 40 global; # TODO: per-port width
+    cost 128;
+    init no_undef;
+    # the following is subject to change as more is implemented in nextpnr-mistral
+    port sw "W" {
+        clock posedge;
+        wrtrans "R" old;
+    }
+    port sr "R" {
+        clock posedge;
+        rden;
+        rdinit zero;
+    }
+}

techlibs/intel_alm/common/bram_m10k_map.v

@@ -1,26 +1,26 @@
 // Stub to invert M10K write-enable.
 
-module \$__MISTRAL_M10K (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+module \$__MISTRAL_M10K (PORT_W_CLK, PORT_W_ADDR, PORT_W_WR_DATA, PORT_W_WR_EN, PORT_R_CLK, PORT_R_ADDR, PORT_R_RD_DATA, PORT_R_RD_EN);
 
 parameter INIT = 0;
+parameter WIDTH = 10;
 
-parameter CFG_ABITS = 10;
-parameter CFG_DBITS = 10;
+input PORT_W_CLK, PORT_R_CLK;
+input [12:0] PORT_W_ADDR, PORT_R_ADDR;
+input [WIDTH-1:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN, PORT_R_RD_EN;
+output reg [WIDTH-1:0] PORT_R_RD_DATA;
 
-input CLK1;
-input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
-input [CFG_DBITS-1:0] A1DATA;
-input A1EN, B1EN;
-output reg [CFG_DBITS-1:0] B1DATA;
+localparam CFG_ABITS = WIDTH == 40 ? 8 : WIDTH == 20 ? 9 : WIDTH == 10 ? 10 : WIDTH == 5 ? 11 : WIDTH == 2 ? 12 : 13;
 
 // Normal M10K configs use WREN[1], which is negative-true.
 // However, 8x40-bit mode uses WREN[0], which is positive-true.
-wire a1en;
-if (CFG_DBITS == 40)
-    assign a1en = A1EN;
+wire wren;
+if (WIDTH == 40)
+    assign wren = PORT_W_WR_EN;
 else
-    assign a1en = !A1EN;
+    assign wren = !PORT_W_WR_EN;
 
-MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(CFG_DBITS)) _TECHMAP_REPLACE_ (.CLK1(CLK1), .A1ADDR(A1ADDR), .A1DATA(A1DATA), .A1EN(a1en), .B1ADDR(B1ADDR), .B1DATA(B1DATA), .B1EN(B1EN));
+MISTRAL_M10K #(.INIT(INIT), .CFG_ABITS(CFG_ABITS), .CFG_DBITS(WIDTH)) _TECHMAP_REPLACE_ (.CLK1(PORT_W_CLK), .A1ADDR(PORT_W_ADDR), .A1DATA(PORT_W_WR_DATA), .A1EN(wren), .B1ADDR(PORT_R_ADDR), .B1DATA(PORT_R_RD_DATA), .B1EN(PORT_R_RD_EN));
 
 endmodule

techlibs/intel_alm/common/lutram_mlab.txt

@@ -1,18 +1,12 @@
-bram MISTRAL_MLAB
-    init   0   # TODO: Re-enable when Yosys remembers the original filename.
-    abits  5
-    dbits  1
-    groups 2
-    ports  1 1
-    wrmode 1 0
-    # write enable
-    enable 1 0
-    transp 0 0
-    clocks 1 0
-    clkpol 1 1
-endbram
-
-match MISTRAL_MLAB
-    min efficiency 5
-    make_outreg
-endmatch
+ram distributed $__MISTRAL_MLAB {
+    abits 5;
+    width 1;
+    cost 4;
+    init zero; # TODO: MLAB init in nextpnr-mistral
+    prune_rom;
+    port sw "W" {
+        clock posedge;
+    }
+    port ar "R" {
+    }
+}

techlibs/intel_alm/common/lutram_mlab_map.v

@@ -0,0 +1,13 @@
+module \$__MISTRAL_MLAB (PORT_W_CLK, PORT_W_ADDR, PORT_W_WR_DATA, PORT_W_WR_EN, PORT_R_ADDR, PORT_R_RD_DATA);
+
+parameter INIT = 0;
+
+input PORT_W_CLK;
+input [4:0] PORT_W_ADDR, PORT_R_ADDR;
+input [4:0] PORT_W_WR_DATA;
+input PORT_W_WR_EN;
+output reg PORT_R_RD_DATA;
+
+MISTRAL_MLAB _TECHMAP_REPLACE_ (.CLK1(PORT_W_CLK), .A1ADDR(PORT_W_ADDR), .A1DATA(PORT_W_WR_DATA), .A1EN(PORT_W_WR_EN), .B1ADDR(PORT_R_ADDR), .B1DATA(PORT_R_RD_DATA));
+
+endmodule

techlibs/intel_alm/synth_intel_alm.cc

@@ -224,13 +224,20 @@ struct SynthIntelALMPass : public ScriptPass {
 			run("opt_clean");
 		}
 
-		if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
-			run(stringf("memory_bram -rules +/intel_alm/common/bram_%s.txt", bram_type.c_str()));
-			run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
-		}
+		if (check_label("map_ram", "(skip if -nobram)")) {
+			std::string args = "";
+			if (help_mode)
+				args += " [-no-auto-block] [-no-auto-distributed]";
+			else {
+				if (nobram)
+					args += " -no-auto-block";
+				if (nolutram)
+					args += " -no-auto-distributed";
+			}
 
-		if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) {
-			run("memory_bram -rules +/intel_alm/common/lutram_mlab.txt", "(for Cyclone V)");
+			run(stringf("memory_libmap -lib +/intel_alm/common/bram_%s.txt -lib +/intel_alm/common/lutram_mlab.txt %s", bram_type.c_str(), args.c_str()), "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
+			run(stringf("techmap -map +/intel_alm/common/bram_%s_map.v", bram_type.c_str()));
+			run("techmap -map +/intel_alm/common/lutram_mlab_map.v");
 		}
 
 		if (check_label("map_ffram")) {