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Reduce number of warnings #4784

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merged 2 commits into from
Dec 4, 2024
Merged

Reduce number of warnings #4784

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1de5d98
Reduce comparisons of size_t and int
KrystalDelusion Nov 28, 2024
e634e9c
aiger2: Resolve warnings
KrystalDelusion Dec 3, 2024
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7 changes: 2 additions & 5 deletions backends/aiger2/aiger.cc
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Expand Up @@ -262,7 +262,8 @@ struct Index {
if (cell->type.in(ID($gt), ID($ge)))
std::swap(aport, bport);
int carry = cell->type.in(ID($le), ID($ge)) ? CFALSE : CTRUE;
Lit a, b;
Lit a = Writer::EMPTY_LIT;
Lit b = Writer::EMPTY_LIT;
// TODO: this might not be the most economic structure; revisit at a later date
for (int i = 0; i < width; i++) {
a = visit(cursor, aport[i]);
Expand Down Expand Up @@ -664,8 +665,6 @@ struct Index {
struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
typedef unsigned int Lit;

const static Lit CONST_FALSE = 0;
const static Lit CONST_TRUE = 1;
const static constexpr Lit EMPTY_LIT = std::numeric_limits<Lit>::max();

static Lit negate(Lit lit) {
Expand Down Expand Up @@ -802,8 +801,6 @@ struct AigerWriter : Index<AigerWriter, unsigned int, 0, 1> {
};

struct XAigerAnalysis : Index<XAigerAnalysis, int, 0, 0> {
const static int CONST_FALSE = 0;
const static int CONST_TRUE = 0;
const static constexpr int EMPTY_LIT = -1;

XAigerAnalysis()
Expand Down
2 changes: 1 addition & 1 deletion backends/edif/edif.cc
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Expand Up @@ -338,7 +338,7 @@ struct EdifBackend : public Backend {
*f << stringf("\n (property %s (integer %u))", EDIF_DEF(name), val.as_int());
else {
std::string hex_string = "";
for (size_t i = 0; i < val.size(); i += 4) {
for (auto i = 0; i < val.size(); i += 4) {
int digit_value = 0;
if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1;
if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2;
Expand Down
18 changes: 8 additions & 10 deletions frontends/aiger2/xaiger.cc
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Expand Up @@ -198,11 +198,10 @@ struct Xaiger2Frontend : public Frontend {

int ci_counter = 0;
for (uint32_t i = 0; i < no_boxes; i++) {
uint32_t box_inputs, box_outputs, box_id, box_seq;
box_inputs = read_be32(*f);
box_outputs = read_be32(*f);
box_id = read_be32(*f);
box_seq = read_be32(*f);
/* unused box_inputs = */ read_be32(*f);
YS_MAYBE_UNUSED auto box_outputs = read_be32(*f);
/* unused box_id = */ read_be32(*f);
auto box_seq = read_be32(*f);

log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size());
log_assert(box_seq < boxes.size());
Expand Down Expand Up @@ -337,11 +336,10 @@ struct Xaiger2Frontend : public Frontend {
len, ci_num, co_num, pi_num, po_num, no_boxes);

for (uint32_t i = 0; i < no_boxes; i++) {
uint32_t box_inputs, box_outputs, box_id, box_seq;
box_inputs = read_be32(*f);
box_outputs = read_be32(*f);
box_id = read_be32(*f);
box_seq = read_be32(*f);
YS_MAYBE_UNUSED auto box_inputs = read_be32(*f);
/* unused box_outputs = */ read_be32(*f);
/* unused box_id = */ read_be32(*f);
auto box_seq = read_be32(*f);

log("box_seq=%d boxes.size=%d\n", box_seq, (int) boxes.size());
log_assert(box_seq < boxes.size());
Expand Down
10 changes: 5 additions & 5 deletions frontends/ast/ast.cc
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Expand Up @@ -931,21 +931,21 @@ bool AstNode::bits_only_01() const
RTLIL::Const AstNode::bitsAsUnsizedConst(int width)
{
RTLIL::State extbit = bits.back();
while (width > int(bits.size()))
while (width > GetSize(bits))
bits.push_back(extbit);
return RTLIL::Const(bits);
}

RTLIL::Const AstNode::bitsAsConst(int width, bool is_signed)
{
std::vector<RTLIL::State> bits = this->bits;
if (width >= 0 && width < int(bits.size()))
if (width >= 0 && width < GetSize(bits))
bits.resize(width);
if (width >= 0 && width > int(bits.size())) {
if (width >= 0 && width > GetSize(bits)) {
RTLIL::State extbit = RTLIL::State::S0;
if ((is_signed || is_unsized) && !bits.empty())
extbit = bits.back();
while (width > int(bits.size()))
while (width > GetSize(bits))
bits.push_back(extbit);
}
return RTLIL::Const(bits);
Expand Down Expand Up @@ -1029,7 +1029,7 @@ double AstNode::asReal(bool is_signed)
val = const_neg(val, val, false, false, val.size());

double v = 0;
for (size_t i = 0; i < val.size(); i++)
for (auto i = 0; i < val.size(); i++)
// IEEE Std 1800-2012 Par 6.12.2: Individual bits that are x or z in
// the net or the variable shall be treated as zero upon conversion.
if (val.at(i) == RTLIL::State::S1)
Expand Down
2 changes: 1 addition & 1 deletion frontends/ast/genrtlil.cc
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Expand Up @@ -984,7 +984,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
// unallocated enum, ignore
break;
case AST_CONSTANT:
width_hint = max(width_hint, int(bits.size()));
width_hint = max(width_hint, GetSize(bits));
if (!is_signed)
sign_hint = false;
break;
Expand Down
4 changes: 2 additions & 2 deletions frontends/ast/simplify.cc
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Expand Up @@ -3493,7 +3493,7 @@ skip_dynamic_range_lvalue_expansion:;
delete buf;

uint32_t result = 0;
for (size_t i = 0; i < arg_value.size(); i++)
for (auto i = 0; i < arg_value.size(); i++)
if (arg_value.at(i) == RTLIL::State::S1)
result = i + 1;

Expand Down Expand Up @@ -4339,7 +4339,7 @@ replace_fcall_later:;
RTLIL::Const a = children[1]->bitsAsConst(width_hint, sign_hint);
RTLIL::Const b = children[2]->bitsAsConst(width_hint, sign_hint);
log_assert(a.size() == b.size());
for (size_t i = 0; i < a.size(); i++)
for (auto i = 0; i < a.size(); i++)
if (a[i] != b[i])
a.bits()[i] = RTLIL::State::Sx;
newNode = mkconst_bits(a.to_bits(), sign_hint);
Expand Down
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