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rp2xxx: enable all riscv features (#358)
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tact1m4n3 authored Jan 23, 2025
1 parent ae1d2e1 commit 6c91a35
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Showing 3 changed files with 4 additions and 9 deletions.
7 changes: 3 additions & 4 deletions port/raspberrypi/rp2xxx/build.zig
Original file line number Diff line number Diff line change
Expand Up @@ -82,16 +82,15 @@ pub fn init(dep: *std.Build.Dependency) Self {
.cpu = std.Target.Query{
.cpu_arch = .riscv32,
.cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
// the commented ones are in the datasheet but for some reason they break the code
.cpu_features_add = std.Target.riscv.featureSet(&.{
// std.Target.riscv.Feature.c,
std.Target.riscv.Feature.a,
std.Target.riscv.Feature.m,
std.Target.riscv.Feature.c,
std.Target.riscv.Feature.zba,
std.Target.riscv.Feature.zbb,
std.Target.riscv.Feature.zbs,
// std.Target.riscv.Feature.zcb,
// std.Target.riscv.Feature.zcmp,
std.Target.riscv.Feature.zcb,
std.Target.riscv.Feature.zcmp,
std.Target.riscv.Feature.zbkb,
std.Target.riscv.Feature.zifencei,
}),
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4 changes: 0 additions & 4 deletions port/raspberrypi/rp2xxx/src/hal/clocks/common.zig
Original file line number Diff line number Diff line change
Expand Up @@ -256,13 +256,9 @@ fn busy_wait_at_least(delay_cycles: u32) void {
\\bcs 1b
,
.riscv =>
\\.option push
\\.option norvc
\\.p2align 2
\\1:
\\addi %[cycles], %[cycles], -2
\\bgez %[cycles], 1b
\\.option pop
,
}
: [cycles] "+r" (_cycles),
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2 changes: 1 addition & 1 deletion port/raspberrypi/rp2xxx/src/hal/image_def.zig
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ const Cpu = enum(u3) {
riscv = 1,
};

const security: Security = if (@hasDecl(app, "image_def_security")) app.image_def_security else .non_secure;
const security: Security = if (@hasDecl(app, "image_def_security")) app.image_def_security else .secure;
const cpu: Cpu = std.meta.stringToEnum(Cpu, @tagName(arch)).?;

const image_def = init();
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