chore: fix some typos in comment (#532)

Signed-off-by: linchizhen <jiayanbing@yeah.net>

tracer/src/emulator/cpu.rs

@@ -301,7 +301,7 @@ impl Cpu {
         self.clock = self.clock.wrapping_add(1);
 
         // cpu core clock : mtime clock in clint = 8 : 1 is
-        // just an arbiraty ratio.
+        // just an arbitrary ratio.
         // @TODO: Implement more properly
         self.write_csr_raw(CSR_CYCLE_ADDRESS, self.clock * 8);
     }

tracer/src/emulator/device/plic.rs

@@ -38,7 +38,7 @@ impl Plic {
 
     /// Runs one cycle. Takes interrupting signals from devices and
     /// raises an interrupt to CPU depending on configuration.
-    /// If interrupt occurs a certain bit of `mip` regiser is risen
+    /// If interrupt occurs a certain bit of `mip` register is risen
     /// depending on interrupt type.
     ///
     /// # Arguments

tracer/src/emulator/device/uart.rs

@@ -53,7 +53,7 @@ impl Uart {
         let mut rx_ip = false;
 
         // Reads input.
-        // 0x38400 is just an arbitary number @TODO: Fix me
+        // 0x38400 is just an arbitrary number @TODO: Fix me
         if (self.clock % 0x38400) == 0 && self.rbr == 0 {
             let value = self.terminal.get_input();
             if value != 0 {
@@ -67,7 +67,7 @@ impl Uart {
         }
 
         // Writes output.
-        // 0x10 is just an arbitary number @TODO: Fix me
+        // 0x10 is just an arbitrary number @TODO: Fix me
         if (self.clock % 0x10) == 0 && self.thr != 0 {
             self.terminal.put_byte(self.thr);
             self.thr = 0;
@@ -161,7 +161,7 @@ impl Uart {
             }
             0x10000001 => {
                 if (self.lcr >> 7) == 0 {
-                    // This bahavior isn't written in the data sheet
+                    // This behavior isn't written in the data sheet
                     // but some drivers seem to rely on it.
                     if (self.ier & IER_THREINT_BIT) == 0
                         && (value & IER_THREINT_BIT) != 0

tracer/src/emulator/device/virtio_block_disk.rs

@@ -3,7 +3,7 @@ use crate::emulator::mmu::MemoryWrapper;
 // Based on Virtual I/O Device (VIRTIO) Version 1.1
 // https://docs.oasis-open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.html
 
-// 0x2000 is an arbitary number.
+// 0x2000 is an arbitrary number.
 const MAX_QUEUE_SIZE: u64 = 0x2000;
 
 // To simulate disk access time.

tracer/src/emulator/mmu.rs

@@ -23,7 +23,7 @@ use super::terminal::Terminal;
 
 /// Emulates Memory Management Unit. It holds the Main memory and peripheral
 /// devices, maps address to them, and accesses them depending on address.
-/// It also manages virtual-physical address translation and memoty protection.
+/// It also manages virtual-physical address translation and memory protection.
 /// It may also be said Bus.
 /// @TODO: Memory protection is not implemented yet. We should support.
 pub struct Mmu {
@@ -147,7 +147,7 @@ impl Mmu {
         self.disk.init(data);
     }
 
-    /// Overrides defalut Device tree configuration.
+    /// Overrides default Device tree configuration.
     ///
     /// # Arguments
     /// * `data` DTB binary content

tracer/src/emulator/mod.rs

@@ -22,7 +22,7 @@ use self::terminal::Terminal;
 ///
 /// Sample code to run the emulator.
 /// ```ignore
-/// // Creates an emulator with arbitary terminal
+/// // Creates an emulator with arbitrary terminal
 /// let mut emulator = Emulator::new(Box::new(DefaultTerminal::new()));
 /// // Set up program content binary
 /// emulator.setup_program(program_content);