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Improve indentation of concurrent properties and sequences (veripool#…
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…1836) (veripool#1837) (veripool#1838)

* verilog-mode.el (verilog-property-re, verilog-beg-of-statement, verilog-calc-1):
Concurrent SVA statement pattern-matching learns 'restrict property' and
'cover sequence' expression for proper indentation around those constructs. This
addresses more patterns in IEEE 1800-2017's 'concurrent_sasertion_statement'
grammar.

* tests{,_ok}/indent_assert_property.v:
Add test cases from GitHub user 'pbing'
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acr4 authored Aug 27, 2023
1 parent 3ab6351 commit 0823759
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14 changes: 14 additions & 0 deletions tests/indent_assert_property.v
Original file line number Diff line number Diff line change
Expand Up @@ -23,3 +23,17 @@ end
always @(posedge clk) begin
end
endmodule

// https://github.com/veripool/verilog-mode/issues/1836
module tb1;
a: restrict property (1);
b: assume property (1);
c: assume property (1);
endmodule

// https://github.com/veripool/verilog-mode/issues/1837
module tb2;
a: cover sequence (1);
b: cover property (1);
c: cover property (1);
endmodule
14 changes: 14 additions & 0 deletions tests_ok/indent_assert_property.v
Original file line number Diff line number Diff line change
Expand Up @@ -23,3 +23,17 @@ module myassert(input clk,
always @(posedge clk) begin
end
endmodule

// https://github.com/veripool/verilog-mode/issues/1836
module tb1;
a: restrict property (1);
b: assume property (1);
c: assume property (1);
endmodule

// https://github.com/veripool/verilog-mode/issues/1837
module tb2;
a: cover sequence (1);
b: cover property (1);
c: cover property (1);
endmodule
25 changes: 15 additions & 10 deletions verilog-mode.el
Original file line number Diff line number Diff line change
Expand Up @@ -2556,11 +2556,13 @@ find the errors."
(defconst verilog-assignment-operation-re-2
(concat "\\(.*?\\)" verilog-assignment-operator-re))

;; Loosely related to IEEE 1800's concurrent_assertion_statement
(defconst verilog-concurrent-assertion-statement-re
"\\(\\<\\(assert\\|assume\\|cover\\|restrict\\)\\>\\s-+\\<\\(property\\|sequence\\)\\>\\)\\|\\(\\<assert\\>\\)")

(defconst verilog-label-re (concat verilog-identifier-sym-re "\\s-*:\\s-*"))
(defconst verilog-property-re
(concat "\\(" verilog-label-re "\\)?"
;; "\\(assert\\|assume\\|cover\\)\\s-+property\\>"
"\\(\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(assert\\)"))
(concat "\\(" verilog-label-re "\\)?" verilog-concurrent-assertion-statement-re))

(defconst verilog-no-indent-begin-re
(eval-when-compile
Expand Down Expand Up @@ -2715,7 +2717,6 @@ find the errors."
"\\(\\<fork\\>\\)\\|" ; 7
"\\(\\<if\\>\\)\\|"
verilog-property-re "\\|"
"\\(\\(" verilog-label-re "\\)?\\<assert\\>\\)\\|"
"\\(\\<clocking\\>\\)\\|"
"\\(\\<task\\>\\)\\|"
"\\(\\<function\\>\\)\\|"
Expand Down Expand Up @@ -4843,7 +4844,7 @@ Uses `verilog-scan' cache."
(not (or (looking-at "\\<") (forward-word-strictly -1)))
;; stop if we see an assertion (perhaps labeled)
(and
(looking-at "\\(\\w+\\W*:\\W*\\)?\\(\\<\\(assert\\|assume\\|cover\\)\\>\\s-+\\<property\\>\\)\\|\\(\\<assert\\>\\)")
(looking-at (concat "\\(\\w+\\W*:\\W*\\)?" verilog-concurrent-assertion-statement-re))
(progn
(setq h (point))
(save-excursion
Expand Down Expand Up @@ -6271,12 +6272,16 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
(throw 'nesting 'defun))))

;;
((looking-at "\\<property\\>")
((looking-at "\\<\\(property\\|sequence\\)\\>")
;; *sigh*
;; {assert|assume|cover} property (); are complete
;; and could also be labeled: - foo: assert property
;; but
;; property ID () ... needs endproperty
;; - {assert|assume|cover|restrict} property (); are complete
;; - cover sequence (); is complete
;; and could also be labeled:
;; - foo: assert property
;; - bar: cover sequence
;; but:
;; - property ID () ... needs endproperty
;; - sequence ID () ... needs endsequence
(verilog-beg-of-statement)
(if (looking-at verilog-property-re)
(throw 'continue 'statement) ; We don't need an endproperty for these
Expand Down

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