Counter.vcd

$date
	Mon Nov 25 13:16:42 2019
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module counter_testbench $end
$var wire 4 ! counter2 [3:0] $end
$var wire 4 " counter1 [3:0] $end
$var reg 1 # clk $end
$var reg 1 $ reset $end
$scope module down $end
$var wire 1 # clk $end
$var wire 4 % counter [3:0] $end
$var wire 1 $ reset $end
$var reg 4 & counter_down [3:0] $end
$upscope $end
$scope module up $end
$var wire 1 # clk $end
$var wire 4 ' counter [3:0] $end
$var wire 1 $ reset $end
$var reg 4 ( counter_up [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
b0 (
b0 '
b1111 &
b1111 %
1$
0#
b0 "
b1111 !
$end
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