Sbsa Errata Changes 625 and 657 (ARM-software#463)

* Sbsa Errata Mantis - 625 -The Rule S_L4SM_01 and S_L4SM_02 is updated -The test for the above rule will fail if no SMMU is present Signed-off-by: Ajayswar S <ajayswar.s@arm.com> * Sbsa Errata Mantis - 657 -The rule S_L6SM_01 is replaced with S_L4SM_03 at level 4 Signed-off-by: Ajayswar S <ajayswar.s@arm.com> --------- Signed-off-by: Ajayswar S <ajayswar.s@arm.com>
ajayswar-s · May 21, 2024 · 70d5177 · 70d5177
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Showing 3 changed files with 7 additions and 13 deletions.
diff --git a/docs/arm_sbsa_testcase_checklist.rst b/docs/arm_sbsa_testcase_checklist.rst
@@ -131,7 +131,7 @@ The below table provides the following details
 +-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
 |312    |Check SMMU Endianess Support                |L6   |B_SMMU_14                                           |Yes             |Yes |Yes       |No   |No                 |
 +-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
-|313    |Check SMMU Coherent Access Support          |L6   |S_L6SM_01                                           |Yes             |Yes |Yes       |No   |No                 |
+|313    |Check SMMU Coherent Access Support          |L4   |S_L4SM_03                                           |Yes             |Yes |Yes       |No   |No                 |
 +-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
 |314    |Check SMMU PMU Extension                    |L7   |S_L7SM_03, S_L7SM_04                                |Yes             |Yes |Yes       |No   |No                 |
 +-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+

diff --git a/test_pool/smmu/operating_system/test_i001.c b/test_pool/smmu/operating_system/test_i001.c
@@ -37,7 +37,7 @@ payload(void)
 
     if (num_smmu == 0) {
         val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
-        val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
         return;
     }
 
@@ -47,31 +47,25 @@ payload(void)
             val_print(ACS_PRINT_ERR,
                      "\n       SMMUv3, or higher must be supported by level 4 or higher systems",
                         0);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
             return;
         } else {
             val_print(ACS_PRINT_INFO, "\n       Detected SMMUv3, or higher implementation ", 0);
             data = val_smmu_read_cfg(SMMUv3_IDR0, num_smmu);
             /* Check Stage 2 translation support */
             if ((data & BIT0) == 0) {
                 val_print(ACS_PRINT_ERR, "\n       Stage 2 translation not supported ", 0);
-                val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+                val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
                 return;
             }
 
             /* Check Stage 1 translation support */
             if ((data & BIT1) == 0) {
                 val_print(ACS_PRINT_ERR, "\n       Stage 1 translation not supported ", 0);
-                val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
-                return;
-            }
-
-            /* Check I/O coherent, (SMMU_IDR0.COHACC == 1) */
-            if ((data & BIT4) == 0) {
-                val_print(ACS_PRINT_ERR, "\n       IO-Coherent access not supported  ", 0);
                 val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
                 return;
             }
+
         }
     }
 

diff --git a/test_pool/smmu/operating_system/test_i013.c b/test_pool/smmu/operating_system/test_i013.c
@@ -22,7 +22,7 @@
 #include "val/sbsa/include/sbsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_SMMU_TEST_NUM_BASE + 13)
-#define TEST_RULE  "S_L6SM_01"
+#define TEST_RULE  "S_L4SM_03"
 #define TEST_DESC  "Check SMMU Coherent Access Support    "
 
 static
@@ -34,7 +34,7 @@ payload(void)
   uint32_t num_smmu;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
-  if (g_sbsa_level < 6) {
+  if (g_sbsa_level < 4) {
       val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
       return;
   }