Adding Primary PE Debug Prints for all PE tests

Signed-off-by: Ajayswar S <ajayswar.s@arm.com>

test_pool/pe/operating_system/test_c001.c

@@ -42,6 +42,15 @@ payload(void)
    *    Check For TGran4_2[43:40] == 0x2 or 0x3 & TGran64_2[39:36] == 0x2.
    */
 
+  val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.TGran4 = %llx",
+                                            VAL_EXTRACT_BITS(data, 28, 31), index);
+  val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.TGran64 = %llx",
+                                            VAL_EXTRACT_BITS(data, 24, 27), index);
+  val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.TGran4_2 = %llx",
+                                            VAL_EXTRACT_BITS(data, 40, 43), index);
+  val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.TGran64_2 = %llx \n",
+                                            VAL_EXTRACT_BITS(data, 36, 39), index);
+
   if (VAL_EXTRACT_BITS(data, 36, 43) == 0) {
     /* Implementation before Arm v8.5 */
     if (VAL_EXTRACT_BITS(data, 24, 31) == 0)

test_pool/pe/operating_system/test_c002.c

@@ -32,6 +32,9 @@ payload(void)
 
   data = val_pe_reg_read(ID_AA64MMFR0_EL1);
 
+  val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.ASIDBits = %llx",
+                                            VAL_EXTRACT_BITS(data, 4, 7), index);
+
   if (data & 0x0020) //bits 7:4 == 0010
 	val_set_status(index, RESULT_PASS(TEST_NUM, 01));
   else

test_pool/pe/operating_system/test_c003.c

@@ -32,6 +32,8 @@ payload(void)
 
   data = val_pe_reg_read(ID_AA64PFR0_EL1);
 
+  val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1 = %llx", data, index);
+
   /* bits 1:0, 5:4, 9:8 and 13:12 must not be zero */
   if ((data & 0x3) && (data & 0x30) && (data & 0x300) && (data & 0x3000))
       val_set_status(index, RESULT_PASS(TEST_NUM, 01));

test_pool/pe/operating_system/test_c004.c

@@ -40,6 +40,11 @@ static void payload(void)
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 0, 3);
     peri_count = val_peripheral_get_info(NUM_ALL, 0);
 
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.PARange = %llx",
+                                            VAL_EXTRACT_BITS(data, 0, 3), index);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       Total Peripherals: %llx", peri_count, index);
+
+
     if (data == FEAT_LPA_IMPL)
     {
         /* If the PE implements FEAT_LPA Index through Peripheral info table and
@@ -51,6 +56,8 @@ static void payload(void)
             /* If the base address is greater than 48 bits it is outside 256TB memory map */
             if (IS_ADDR_EXCEEDS_48BITS(peri_base))
             {
+                val_print_primary_pe(ACS_PRINT_DEBUG,
+                         "\n       Peripheral Address %llx exceeds 48 bits", peri_base, index);
                 val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
                 return;
             }

test_pool/pe/operating_system/test_c005.c

@@ -37,6 +37,8 @@ void payload(void)
     /* Read ID_AA64PFR0_EL1[31:28] For RAS Extensions */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 28, 31);
 
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1.RAS = %llx", data, index);
+
     if (data == 0x0)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
     else

test_pool/pe/operating_system/test_c006.c

@@ -39,12 +39,15 @@ static void payload(void)
         /* ID_AA64ISAR1_EL1.DPB[3:0] = 0b0001 or 0b0010 indicate support for
            DC CVAP instruction */
         data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 0, 3);
+        val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.DPB = %llx", data, index);
+
         if (data == 0b0001 || data == 0b0010)
             val_set_status(index, RESULT_PASS(TEST_NUM, 01));
         else
             val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
         return;
     }
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       No Persistent Memory Exists \n", 0, index);
     val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
 }
 

test_pool/pe/operating_system/test_c007.c

@@ -36,6 +36,9 @@ static void payload(void)
 
     /* Read ID_AA64MMFR1_EL1[7:4] For VMID */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 4, 7);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR1_EL1.VMIDBits = %llx",
+                                                                         data, index);
+
 
     if (data == 0x2)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));

test_pool/pe/operating_system/test_c008.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64MMFR1_EL1[11:8] For VH */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 8, 11);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR1_EL1.VH = %llx", data, index);
+
 
     if (data == 0x1)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));

test_pool/pe/operating_system/test_c009.c

@@ -37,6 +37,8 @@ static void payload(void)
      * support using level 1 or level 2
      */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 52, 55);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR2_EL1.BBM = %llx", data, index);
+
     if ((data == 0x1) || (data == 0x2))
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));
     else

test_pool/pe/operating_system/test_c010.c

@@ -42,22 +42,19 @@ static void check_pointer_signing_algorithm(uint32_t index, uint64_t data1, uint
 static void payload(void)
 {
     uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-    uint32_t primary_pe_idx = val_pe_get_primary_index();
 
     /* Read ID_AA64ISAR1_EL1 and ID_AA64ISAR2_EL1 for PAuth support */
     uint64_t data1 = val_pe_reg_read(ID_AA64ISAR1_EL1);
     uint64_t data2 = val_pe_reg_read(ID_AA64ISAR2_EL1);
 
-    if (index == primary_pe_idx) {
-       val_print(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.APA[7:4]    = %llx",
-                 VAL_EXTRACT_BITS(data1, 4, 7));
-       val_print(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.GPA[27:24]  = %llx",
-                 VAL_EXTRACT_BITS(data1, 24, 27));
-       val_print(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR2_EL1.APA3[15:12] = %llx",
-                 VAL_EXTRACT_BITS(data2, 12, 15));
-       val_print(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR2_EL1.GPA3[11:8]  = %llx",
-                 VAL_EXTRACT_BITS(data2, 8, 11));
-    }
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.APA[7:4]    = %llx",
+                 VAL_EXTRACT_BITS(data1, 4, 7), index);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.GPA[27:24]  = %llx",
+                 VAL_EXTRACT_BITS(data1, 24, 27), index);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR2_EL1.APA3[15:12] = %llx",
+                 VAL_EXTRACT_BITS(data2, 12, 15), index);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR2_EL1.GPA3[11:8]  = %llx",
+                 VAL_EXTRACT_BITS(data2, 8, 11), index);
 
     if (g_sbsa_level < 5) {
         val_set_status(index, RESULT_SKIP(TEST_NUM, 01));

test_pool/pe/operating_system/test_c011.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64PFR0_EL1[47:44] for Activity monitors extension */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 44, 47);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1.AMU = %llx", data, index);
+
     if (data != 0)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));
     else

test_pool/pe/operating_system/test_c012.c

@@ -41,15 +41,19 @@ static void payload(void)
 
     /* Read ID_AA64ISAR0_EL1.SHA3[35:32] for cryptography support for SHA3 */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 32, 35);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR0_EL1.SHA3 = %llx", data, index);
+
     if (data == 0x1)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));
     else {
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
         return;
     }
 
-    /* Read ID_AA64ISAR0_EL1.SHA3[15:12] for cryptography support for SHA512 */
+    /* Read ID_AA64ISAR0_EL1.SHA2[15:12] for cryptography support for SHA512 */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 12, 15);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR0_EL1.SHA2 = %llx", data, index);
+
     if (data == 0x2)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));
     else

test_pool/pe/operating_system/test_c013.c

@@ -35,6 +35,8 @@ static void payload(void)
 
     /* Read ID_AA64MMFR2_EL1.FWB[43:40] for stage 2 control of memory types and cacheability */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 40, 43);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR2_EL1.FWB = %llx", data, index);
+
     if (data == 0x1)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));
     else

test_pool/pe/operating_system/test_c014.c

@@ -27,7 +27,6 @@ static void payload(void)
 {
     uint64_t data = 0;
     uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-    uint32_t primary_pe_idx = val_pe_get_primary_index();
 
     if (g_sbsa_level < 5) {
         val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
@@ -36,9 +35,8 @@ static void payload(void)
 
     /* Read ID_AA64MMFR2_EL1[27:24] for enhanced Nested Virtualization support */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 24, 27);
-    if (index == primary_pe_idx) {
-        val_print(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR2_EL1.NV  = %llx", data);
-    }
+
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR2_EL1.NV  = %llx", data, index);
 
     /* Read ID_AA64MMFR2_EL1.NV[27:24] == 2 indicates FEAT_NV2 support
      * Value 1 indicates FEAT_NV support

test_pool/pe/operating_system/test_c015.c

@@ -38,6 +38,13 @@ static void payload(void)
     /* ID_AA64PFR0_EL1.MPAM bits[43:40] > 0 or ID_AA64PFR1_EL1.MPAM_frac bits[19:16] > 0
        indicates implementation of MPAM extension */
 
+    data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1.MPAM = %llx", data, index);
+
+    data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR1_EL1.MPAM_frac = %llx",
+                                                                       data, index);
+
     if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) ||
         (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) {
             val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
@@ -47,13 +54,16 @@ static void payload(void)
     /* check support for minimum of 16 physical partition IDs, MPAMIDR_EL1.PARTID_MAX
        must be >= 16 */
     data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 0, 15);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       MPAMIDR_EL1.PARTID_MAX = %llx", data, index);
+
     if (data < 16) {
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
         return;
     }
 
     /* check support for MPAM virtulization support indicated by MPAMIDR_EL1.HAS_HCR bit */
     data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 17, 17);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       MPAMIDR_EL1.HAS_HCR = %llx", data, index);
     if (data == 0) {
         val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
         return;
@@ -62,6 +72,8 @@ static void payload(void)
     /* check support for minimum of 8 virtual partition IDs,
        MPAMIDR_EL1.VPMR_MAX must be > 0 */
     data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 18, 20);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       MPAMIDR_EL1.VPMR_MAX = %llx", data, index);
+
     if (data < 1) {
         val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
         return;
@@ -70,6 +82,7 @@ static void payload(void)
     /* Check support for minimum of 2 performance monitor groups (PMGs),
     MPAMIDR_EL1.PMG_MAX must be >= 1 (value of PMG.MAX 1 means PMG 0 and 1 present */
     data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 32, 39);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       MPAMIDR_EL1.PMG_MAX = %llx", data, index);
     if (data < 1) {
         val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
         return;

test_pool/pe/operating_system/test_c016.c

@@ -48,13 +48,22 @@ static void payload(void)
     uint32_t memside_llc_cpor_supported = 0;
     uint64_t desc1;
     uint64_t desc2;
+    uint64_t data = 0;
 
     if (g_sbsa_level < 5) {
         val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
         return;
     }
 
     /* If PE not implements FEAT_MPAM, Skip the test */
+    data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1.MPAM = %llx", data, index);
+
+    data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR1_EL1.MPAM_frac = %llx",
+                                                                           data, index);
+
+
     if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) ||
         (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) {
             val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
@@ -64,10 +73,9 @@ static void payload(void)
     /* If MPAM table not present, or no MSC
        found in table fail the test */
     msc_node_cnt = val_mpam_get_msc_count();
-    val_print(ACS_PRINT_DEBUG, "\n       MSC count = %d", msc_node_cnt);
+    val_print(ACS_PRINT_ERR, "\n       MSC count = %d", msc_node_cnt);
 
     if (msc_node_cnt == 0) {
-        val_print(ACS_PRINT_ERR, "\n       MSC count is 0", 0);
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
         return;
     }

test_pool/pe/operating_system/test_c017.c

@@ -29,7 +29,6 @@ void payload(void)
 {
     uint64_t data = 0;
     uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-    uint32_t primary_pe_idx = val_pe_get_primary_index();
 
     if (g_sbsa_level < 6) {
         val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
@@ -38,8 +37,7 @@ void payload(void)
 
     /* Read ID_AA64PFR0_EL1.SVE[35:32] = 0b0001 for SVE */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 32, 35);
-    if (index == primary_pe_idx)
-        val_print(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1.SVE = %llx", data);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR0_EL1.SVE = %llx", data, index);
 
     if (data == 0) {
         /* SVE Not Implemented Skip the test */
@@ -49,8 +47,7 @@ void payload(void)
 
     /* Read ID_AA64DFR0_EL1.PMSVer[35:32] = 0b0010 for v8.3-SPE */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 32, 35);
-    if (index == primary_pe_idx)
-        val_print(ACS_PRINT_DEBUG, "\n       ID_AA64DFR0_EL1.PMSVer = %llx", data);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64DFR0_EL1.PMSVer = %llx", data, index);
 
     if (data < 2)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c018.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64PFR1_EL1.BT[3:0] = 0b0001 For Branch Target Identification Support */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 0, 3);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR1_EL1.BT = %llx", data, index);
+
 
     if (data != 1)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c019.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64MMFR2_EL1.E0PD[63:60] = 0b0001 For Support for Protect Against Timing Fault */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 60, 63);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR2_EL1.E0PD = %llx", data, index);
+
 
     if (data != 1)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c021.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64MMFR1_EL1.HAFDBS[3:0] = 0b0010 For Hardware update supported */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 0, 3);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR1_EL1.HAFDBS = %llx", data, index);
+
 
     if (data != 2)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c022.c

@@ -36,6 +36,7 @@ static void payload(void)
 
     /* ID_AA64MMFR2_EL1.EVT[59:56] = 0b0010 - Support for Enhanced Virtualization Trap */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 56, 59);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR2_EL1.EVT = %llx", data, index);
 
     if (data != 2)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c024.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64PFR1_EL1.SSBS[7:4] = 0b0010 */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR1_EL1.SSBS = %llx", data, index);
+
 
     if (data != 2)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c025.c

@@ -33,6 +33,8 @@ payload()
 
     /* Read ID_AA64PFR1_EL1[7:4] != 0 For CSDB, SSBB and PSSBB barriers  */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64PFR1_EL1 = %llx", data, index);
+
 
     if (data == 0)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 1));

test_pool/pe/operating_system/test_c026.c

@@ -36,6 +36,7 @@ static void payload(void)
 
     /* Read ID_AA64ISAR1_EL1.SB[39:36] = 0b0001 For SB Speculation Barrier */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 36, 39);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.SB = %llx", data, index);
 
     if (data != 1)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c027.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /* Read ID_AA64ISAR1_EL1.SPECRES[43:40] = 0b0001 For CFP, DVP, CPP RCTX Instructions */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 40, 43);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64ISAR1_EL1.SPECRES = %llx", data, index);
+
 
     if (data != 1)
         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));

test_pool/pe/operating_system/test_c028.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /*  ID_AA64MMFR0_EL1.FGT[59:56] = 0b0001 indicate fine grained trap feature */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 56, 59);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.FGT = %llx", data, index);
+
 
     if (data == 1)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));

test_pool/pe/operating_system/test_c029.c

@@ -36,6 +36,8 @@ static void payload(void)
 
     /*  ID_AA64MMFR0_EL1.ECV[63:60] = 0b0010 indicate Enhanced counter vitualization */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 60, 63);
+    val_print_primary_pe(ACS_PRINT_DEBUG, "\n       ID_AA64MMFR0_EL1.ECV = %llx", data, index);
+
 
     if (data == 2)
         val_set_status(index, RESULT_PASS(TEST_NUM, 01));