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Make resp and prot signals optional
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alexforencich committed Apr 13, 2021
1 parent e7c3a31 commit bc7edec
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Showing 4 changed files with 34 additions and 12 deletions.
16 changes: 8 additions & 8 deletions cocotbext/axi/axi_channels.py
Original file line number Diff line number Diff line change
Expand Up @@ -26,8 +26,8 @@

# Write address channel
AxiAWBus, AxiAWTransaction, AxiAWSource, AxiAWSink, AxiAWMonitor = define_stream("AxiAW",
signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awprot", "awvalid", "awready"],
optional_signals=["awlock", "awcache", "awqos", "awregion", "awuser"],
signals=["awid", "awaddr", "awlen", "awsize", "awburst", "awvalid", "awready"],
optional_signals=["awlock", "awcache", "awprot", "awqos", "awregion", "awuser"],
signal_widths={"awlen": 8, "awsize": 3, "awburst": 2, "awlock": 1,
"awcache": 4, "awprot": 3, "awqos": 4, "awregion": 4}
)
Expand All @@ -41,23 +41,23 @@

# Write response channel
AxiBBus, AxiBTransaction, AxiBSource, AxiBSink, AxiBMonitor = define_stream("AxiB",
signals=["bid", "bresp", "bvalid", "bready"],
optional_signals=["buser"],
signals=["bid", "bvalid", "bready"],
optional_signals=["bresp", "buser"],
signal_widths={"bresp": 2}
)

# Read address channel
AxiARBus, AxiARTransaction, AxiARSource, AxiARSink, AxiARMonitor = define_stream("AxiAR",
signals=["arid", "araddr", "arlen", "arsize", "arburst", "arprot", "arvalid", "arready"],
optional_signals=["arlock", "arcache", "arqos", "arregion", "aruser"],
signals=["arid", "araddr", "arlen", "arsize", "arburst", "arvalid", "arready"],
optional_signals=["arlock", "arcache", "arprot", "arqos", "arregion", "aruser"],
signal_widths={"arlen": 8, "arsize": 3, "arburst": 2, "arlock": 1,
"arcache": 4, "arprot": 3, "arqos": 4, "arregion": 4}
)

# Read data channel
AxiRBus, AxiRTransaction, AxiRSource, AxiRSink, AxiRMonitor = define_stream("AxiR",
signals=["rid", "rdata", "rresp", "rlast", "rvalid", "rready"],
optional_signals=["ruser"],
signals=["rid", "rdata", "rlast", "rvalid", "rready"],
optional_signals=["rresp", "ruser"],
signal_widths={"rresp": 2, "rlast": 1}
)

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8 changes: 8 additions & 0 deletions cocotbext/axi/axi_master.py
Original file line number Diff line number Diff line change
Expand Up @@ -177,6 +177,7 @@ def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_le

self.awlock_present = hasattr(self.bus.aw, "awlock")
self.awcache_present = hasattr(self.bus.aw, "awcache")
self.awprot_present = hasattr(self.bus.aw, "awprot")
self.awqos_present = hasattr(self.bus.aw, "awqos")
self.awregion_present = hasattr(self.bus.aw, "awregion")
self.awuser_present = hasattr(self.bus.aw, "awuser")
Expand Down Expand Up @@ -240,6 +241,9 @@ def init_write(self, address, data, awid=None, burst=AxiBurstType.INCR, size=Non
if not self.awcache_present and cache != 0b0011:
raise ValueError("awcache sideband signal value specified, but signal is not connected")

if not self.awprot_present and prot != AxiProt.NONSECURE:
raise ValueError("awprot sideband signal value specified, but signal is not connected")

if not self.awqos_present and qos != 0:
raise ValueError("awqos sideband signal value specified, but signal is not connected")

Expand Down Expand Up @@ -558,6 +562,7 @@ def __init__(self, bus, clock, reset=None, reset_active_level=True, max_burst_le

self.arlock_present = hasattr(self.bus.ar, "arlock")
self.arcache_present = hasattr(self.bus.ar, "arcache")
self.arprot_present = hasattr(self.bus.ar, "arprot")
self.arqos_present = hasattr(self.bus.ar, "arqos")
self.arregion_present = hasattr(self.bus.ar, "arregion")
self.aruser_present = hasattr(self.bus.ar, "aruser")
Expand Down Expand Up @@ -622,6 +627,9 @@ def init_read(self, address, length, arid=None, burst=AxiBurstType.INCR, size=No
if not self.arcache_present and cache != 0b0011:
raise ValueError("arcache sideband signal value specified, but signal is not connected")

if not self.arprot_present and prot != AxiProt.NONSECURE:
raise ValueError("arprot sideband signal value specified, but signal is not connected")

if not self.arqos_present and qos != 0:
raise ValueError("arqos sideband signal value specified, but signal is not connected")

Expand Down
12 changes: 8 additions & 4 deletions cocotbext/axi/axil_channels.py
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,8 @@

# Write address channel
AxiLiteAWBus, AxiLiteAWTransaction, AxiLiteAWSource, AxiLiteAWSink, AxiLiteAWMonitor = define_stream("AxiLiteAW",
signals=["awaddr", "awprot", "awvalid", "awready"],
signals=["awaddr", "awvalid", "awready"],
optional_signals=["awprot"],
signal_widths={"awprot": 3}
)

Expand All @@ -37,19 +38,22 @@

# Write response channel
AxiLiteBBus, AxiLiteBTransaction, AxiLiteBSource, AxiLiteBSink, AxiLiteBMonitor = define_stream("AxiLiteB",
signals=["bresp", "bvalid", "bready"],
signals=["bvalid", "bready"],
optional_signals=["bresp"],
signal_widths={"bresp": 2}
)

# Read address channel
AxiLiteARBus, AxiLiteARTransaction, AxiLiteARSource, AxiLiteARSink, AxiLiteARMonitor = define_stream("AxiLiteAR",
signals=["araddr", "arprot", "arvalid", "arready"],
signals=["araddr", "arvalid", "arready"],
optional_signals=["arprot"],
signal_widths={"arprot": 3}
)

# Read data channel
AxiLiteRBus, AxiLiteRTransaction, AxiLiteRSource, AxiLiteRSink, AxiLiteRMonitor = define_stream("AxiLiteR",
signals=["rdata", "rresp", "rvalid", "rready"],
signals=["rdata", "rvalid", "rready"],
optional_signals=["rresp"],
signal_widths={"rresp": 2}
)

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10 changes: 10 additions & 0 deletions cocotbext/axi/axil_master.py
Original file line number Diff line number Diff line change
Expand Up @@ -79,6 +79,8 @@ def __init__(self, bus, clock, reset=None, reset_active_level=True):
self.byte_lanes = self.width // self.byte_size
self.strb_mask = 2**self.byte_lanes-1

self.awprot_present = hasattr(self.bus.aw, "awprot")

self.log.info("AXI lite master configuration:")
self.log.info(" Address width: %d bits", len(self.aw_channel.bus.awaddr))
self.log.info(" Byte size: %d bits", self.byte_size)
Expand Down Expand Up @@ -107,6 +109,9 @@ def init_write(self, address, data, prot=AxiProt.NONSECURE, event=None):
if not isinstance(event, Event):
raise ValueError("Expected event object")

if not self.awprot_present and prot != AxiProt.NONSECURE:
raise ValueError("awprot sideband signal value specified, but signal is not connected")

self.in_flight_operations += 1
self._idle.clear()

Expand Down Expand Up @@ -311,6 +316,8 @@ def __init__(self, bus, clock, reset=None, reset_active_level=True):
self.byte_size = 8
self.byte_lanes = self.width // self.byte_size

self.arprot_present = hasattr(self.bus.ar, "arprot")

self.log.info("AXI lite master configuration:")
self.log.info(" Address width: %d bits", len(self.ar_channel.bus.araddr))
self.log.info(" Byte size: %d bits", self.byte_size)
Expand Down Expand Up @@ -338,6 +345,9 @@ def init_read(self, address, length, prot=AxiProt.NONSECURE, event=None):
if not isinstance(event, Event):
raise ValueError("Expected event object")

if not self.arprot_present and prot != AxiProt.NONSECURE:
raise ValueError("arprot sideband signal value specified, but signal is not connected")

self.in_flight_operations += 1
self._idle.clear()

Expand Down

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