v0.2.14

Notable changes in this release:

Simulation models:

• Fix some bugs related to devices with multiple functions
• Improve max latency timer computation based on PCIe spec
• Fix typo in Tlp.unpack_header()
• Fix link control register bits
• Fix ERR_FATAL message type
• Add PTM message types
• Support splitting read requests on every RCB
• Implement CRS software visibility
• For downstream ports, only enumerate device 0
• Handle CRS during enumeration

IP core models:

• Fix logging when using from_entity() in P-Tile, S10, and US/US+ models
• Add P-Tile port number
• Enforce RX completion buffer occupancy in P-Tile, S10, and US/US+ models
• Fix cfg_rcb_status in US/US+ models
• Add local error reporting in US/US+ models
• Update S10, P-Tile, and US/US+ models based on RX completion buffer tests

0.2.12

Notable changes in this release:

Simulation models:

• Support issuing non-posted operations in parallel

IP core models:

• Fix RcSink discontinue bit offset in US/US+ models
• Improve tag handling in US/US+ models
• Improve tag handling in Intel models
• Refactor bus master enable and discontinue checks in US/US+ models
• Add support for internal core tag management in US/US+ models
• Pause US/US+ sources and sinks when idle

0.2.10

Notable changes in this release:

• Widen flow control counters and mask off appropriately so P-Tile model can report the correct values

0.2.8

Notable changes in this release:

IP core models:

• Add PCIe HIP model for Intel Stratix 10 DX/Agilex P-Tile

0.2.6

Notable changes in this release:

IP core models:

• Fix framing for 256 bit RC interface when TLP straddling is enabled in UltraScale model

0.2.4

Notable changes in this release:

IP core models:

• Fix handling of byte enable and sequence number in RQ tuser sideband when TLP straddling is enabled in UltraScale+ model

v0.2.2

Notable changes in this release:

Simulation models:

• Fix IRQ vector min/max range checks
• Properly implement zero-length operations

IP core models:

• Properly implement zero-length operations
• Defer TLP conversion to string when logging
• Implement TLP straddling in Xilinx UltraScale models

0.2.0

Notable changes in this release:

Simulation models:

• Mirror root complex TLP size settings to host bridge
• Transfer configuration from upstream bridge to new switch ports
• New system software abstraction
• Support MSI-X

IP core models:

• Improve PF and MSI configuration
• Properly propagate extended tag support setting
• Add extended tag configuration to Stratix 10 model
• Add max payload size configuration options to device models
• Support MSI-X in device models

0.1.22

Notable changes in this release:

Simulation models:

• Clean up simulation time handling
• Use start_soon instead of fork
• Test on python 3.10
• Fix bridge prefetchable base/limit registers
• Fix config space register region checks

IP core models:

• Log interrupt requests
• Cache clock edge event objects

0.1.20

Notable changes in this release:

Simulation models:

• Logging performance improvements
• Clean up BAR matching and TLP handling
• Include TLP in error logs
• Alias upstream port PCIe ID on PCIe switch
• Use address space abstraction