GitHub - algorhtym/uart-design: Structural VHDL Implementation of a Universal Asynchronous Receiver Transmitter (UART) Design Project as part of a Digital Systems course

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Structural VHDL Implementation of a Universal Asynchronous Receiver Transmitter (UART) Design Project as part of a Digital Systems course

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Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
comparator_4bit.vhd		comparator_4bit.vhd
dFF_2.vhd		dFF_2.vhd
dflipflop.vhd		dflipflop.vhd
dlatch.vhd		dlatch.vhd
mod16counter.vhd		mod16counter.vhd
onebitcomparator.vhd		onebitcomparator.vhd
tFF_2.vhd		tFF_2.vhd
tdr.vhd		tdr.vhd
tdr_TB.vhd		tdr_TB.vhd
tsr.vhd		tsr.vhd
tsr_TB.vhd		tsr_TB.vhd
tx_control.vhd		tx_control.vhd
tx_control_tb.vhd		tx_control_tb.vhd
tx_fsm.vhd		tx_fsm.vhd
tx_fsm_tb.vhd		tx_fsm_tb.vhd