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python solution:app_upgrade,fixes #1840 #1841

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Jinliang Li and others added 30 commits April 13, 2022 21:13
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
2.delete components/csi

Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
…close source

Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
2.haas700
3.optimize netmgr deinit function of amp
4.close quickjs force GC

Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
Signed-off-by: caiyan.cai <caiyan.cai@alibaba-inc.com>
wuxn9999 and others added 17 commits June 8, 2022 14:32
[Detail]
Workaround for ethernet spi hardware to prevent dead loops.

[Verified Cases]
Build Pass: <helloworld_demo@haas100>
Test Pass: <helloworld_demo@haas100>
[Detail]
Fix documentation on UART API: on()
Improve examples in UART doc.

[Verified Cases]
Build Pass: None
Test Pass: None
* modify HaaSPython's brief introduction, fix alibaba#1772

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>

* add HaaS Python v2.2.0 release notest, fix alibaba#1726

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>
* modify HaaSPython's brief introduction, fix alibaba#1772

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>

* add HaaS Python v2.2.0 release notest, fix alibaba#1726

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>

* add README for HaaS EDU K1 examples, fix alibaba#1798

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>
* modify HaaSPython's brief introduction, fix alibaba#1772

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>

* add HaaS Python v2.2.0 release notest, fix alibaba#1726

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>

* add chapter index for examples, fix alibaba#1800

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>
[Detail]
improve lwip options to fix http test faults

[Verified Cases]
Build Pass: <py_engine_demo>
Test Pass:  <py_engine_demo>
[Detail]
when CONFIG_FREERTOS_INTERRUPT_BACKTRACE opens, XT_DEBUG_BACKTRACE will open.
opening XT_DEBUG_BACKTRACE can backtrace interrupt callchain of thread context although it usually
useless, but it EXCSAVEx register. if normal exception occurs, which also uses EXCSAVEx register,
        and having tail interrupt after current isr, it will crush EXCSAVEx, then system will crash.
        so based on above, close CONFIG_FREERTOS_INTERRUPT_BACKTRACE.

[Verified Cases]
Build Pass: none
Test Pass: none
…libaba#1719

[Detail]
Issue description:

Rootcause:

Solution:

Requirement description:

Solution:

[Verified Cases]
Build Pass: <solution list>
Test Pass: <test case list>

Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>
Signed-off-by: ethan.lcz <ethan.lcz@alibaba-inc.com>
[Detail]
to open bt on nodemcu32s, need to do things as below.
import kv
kv.set("disable_bt", "no")
然后重启设备

[Verified Cases]
Build Pass: <none>
Test Pass: <none>
… thread stack size and optimise memory layout statics.

[Detail]
on m5stackcore2, with lvgl, linksdk, online update all on,mp_stack stack remains still 3636
when set from 16KB to 8KB.
on m5stackcore2, with lvgl, linksdk, online update all on,queue_handler stack remains still 1776
when set from 8KB to 3KB.
on m5stackcore2, user logic is placed on mp_task, so mqtt_rec's stack remains 1676 should be enough.
mqtt_process only process repub, hearbeat and some event, on m5stackcore2, mqtt_process's stack
remains 1504 should be enough.
for arm and xtensa, stack should be enough based on current sitution
but for esp32_c3 riscv, due to c11 tls, every stack will have another 1KB space, needs to remove it.

[Verified Cases]
Build Pass: <py_engine_esp32_demo>
Test Pass: <py_engine_esp32_demo>
[Detail]
Issue description:

Rootcause:

Solution:

Requirement description:

Solution:

[Verified Cases]
Build Pass: <solution list>
Test Pass: <test case list>

Signed-off-by: wzhiyuan-nit <wuming.wzy@alibaba-inc.com>
[Detail]
hal_uart_recv_II returns 0 if no data received, instead of returning EIO.

[Verified Cases]
Build Pass: eduk1_demo
Test Pass: eduk1_demo
- Use printk instead of printf in mm critical region, otherwise, system
  will crash, specially in SMP system.

- Remove "0x" prefix before "%p", "0x" is redundant for "%p".
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CLAassistant commented Jun 17, 2022

CLA assistant check
All committers have signed the CLA.

@skylarCai
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感谢提交 Pull Requests!
Thanks for submitting a pull request.

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Security Check : b2f7323

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@ZH-21000301 ZH-21000301 left a comment

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python app upgrade

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auto build success,number:228

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autotest fail,number:1712

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@ethanlcz ethanlcz left a comment

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looks good to me.

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looks good to me.

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