CacheDirector

CacheDirector is a network I/O solution that exploits slice-aware memory management, extends Data Direct I/O (DDIO), and sends each packet's header directly to the correct slice in the LLC; hence, the CPU core that is responsible for processing a packet can access the packet header in fewer CPU cycles. For more information, check out our paper and my talk at EuroSys'19.

Building CacheDirector

To build, you can use the default DPDK build system.

make install T=x86_64-native-linuxapp-gcc

The current version of CacheDirector is tested on systems with Intel(R) Xeon(R) E5-2667 v3 and Intel(R) Xeon(R) Gold 6134, which are equipped with Mellanox ConnectX-4 MT27700 card.

Extra Consideration

• Please set CONFIG_RTE_PKTMBUF_HEADROOM according to your CPU architecture. You can find more information in ./config/common_base.
• Please define/undefine HASWELL or SKYLAKE in ./lib/librte_msr/rte_msr.h according to your CPU architecture.
• Please define/undefine UNCORE in ./lib/librte_slice/rte_slice.h for using uncore performance counters, rather than hash function. It is important to notice that hash function only works on Haswell architecture.

Using CacheDirector with FastClick

You can try CacheDirector with any DPDK-based application. However, if you want to use FastClick or Metron. You have to modify $fastclick-path/userlevel/dpdk.mk to support new libraries added for CacheDirector, as below:

ifneq ($(CONFIG_RTE_BUILD_COMBINE_LIBS),y)
_LDLIBS-$(CONFIG_RTE_LIBRTE_MSR)            += -lrte_msr 	  # Added
_LDLIBS-$(CONFIG_RTE_LIBRTE_SLICE)          += -lrte_slice  # Added
_LDLIBS-$(CONFIG_RTE_LIBRTE_KVARGS)         += -lrte_kvargs
_LDLIBS-$(CONFIG_RTE_LIBRTE_MBUF)           += -lrte_mbuf
_LDLIBS-$(CONFIG_RTE_LIBRTE_MBUF_OFFLOAD)   += -lrte_mbuf_offload
_LDLIBS-$(CONFIG_RTE_LIBRTE_IP_FRAG)        += -lrte_ip_frag

Then, you need to configure and make FastClick:

./configure RTE_SDK=$CACHEDIRECTORPATH RTE_TARGET=x86_64-native-linuxapp-gcc --enable-multithread --disable-linuxmodule --enable-intel-cpu --enable-user-multithread --verbose CFLAGS="-std=gnu11 -O3" CXXFLAGS="-std=gnu++14 -O3" --disable-dynamic-linking --enable-poll --enable-bound-port-transfer --enable-dpdk --enable-batch --with-netmap=no --enable-zerocopy --disable-dpdk-pool --disable-dpdk-packet --enable-local --enable-nanotimestamp --enable-ipsec --enable-analysis --disable-ip6 --enable-simple --enable-etherswitch --enable-json --enable-all-elements

make

Building an emulated slice-aware Key-Value Store (KVS)

export RTE_SDK=$CACHEDIRECTOR_PATH
export RTE_TARGET=x86_64-native-linuxapp-gcc
cd examples/KVS
make

Citing our paper

If you use CacheDirector or slice-aware memory management in any context, please cite our paper:

@inproceedings{farshin-slice-aware,
 author = {Farshin, Alireza and Roozbeh, Amir and {Maguire Jr.}, Gerald Q. and Kosti\'{c}, Dejan},
 title = {{Make the Most out of Last Level Cache in Intel Processors}},
 booktitle = {Proceedings of the Fourteenth EuroSys Conference 2019},
 series = {EuroSys '19},
 year = {2019},
 isbn = {978-1-4503-6281-8},
 location = {Dresden, Germany},
 pages = {8:1--8:17},
 articleno = {8},
 numpages = {17},
 url = {http://doi.acm.org/10.1145/3302424.3303977},
 doi = {10.1145/3302424.3303977},
 acmid = {3303977},
 publisher = {ACM},
 address = {New York, NY, USA},
 keywords = {Cache Allocation Technology, Cache Partitioning, CacheDirector, DDIO, DPDK, Key-Value Store, Last Level Cache, Network Function Virtualization, Non-Uniform Cache Architecture, Slice-aware Memory Management},
}

Getting Help

If you have any questions regarding our code or the paper, you can contact Amir Roozbeh (amirrsk at kth.se) and/or Alireza Farshin (farshin at kth.se).