run clang-format

Signed-off-by: Sadik Ozer <sadik.ozer@analog.com>

Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c

@@ -22,14 +22,13 @@
 
 extern uint32_t _application_end;
 
-#define SLA_HEADER_MAGIC0  0xBF1421E4
-#define SLA_HEADER_MAGIC1  0x461A8CF5
-#define SLA_HEADER_VERSION  0x00000001
+#define SLA_HEADER_MAGIC0 0xBF1421E4
+#define SLA_HEADER_MAGIC1 0x461A8CF5
+#define SLA_HEADER_VERSION 0x00000001
 #define SLA_HEADER_ALGORITHM_ECDSA 0x516A0001
-#define SLA_HEADER_RESERVED  0x00000000
+#define SLA_HEADER_RESERVED 0x00000000
 
-typedef struct
-{
+typedef struct {
  uint32_t magic0;
  uint32_t magic1;
  uint32_t version;
@@ -40,16 +39,12 @@ typedef struct
  uint32_t reserved7;
 } flash_app_header_t;
 
-__attribute__ ((section(".sla_header"))) __attribute__ ((__used__))
-const flash_app_header_t sla_header =
-{
- .magic0 = SLA_HEADER_MAGIC0,
- .magic1 = SLA_HEADER_MAGIC1,
- .version = SLA_HEADER_VERSION,
- .verifytype = SLA_HEADER_ALGORITHM_ECDSA,
- .sigaddress = (uint32_t)&_application_end,
- .reserved5 = SLA_HEADER_RESERVED,
- .reserved6 = SLA_HEADER_RESERVED,
- .reserved7 = SLA_HEADER_RESERVED
-};
-
+__attribute__((section(".sla_header"))) __attribute__((__used__))
+const flash_app_header_t sla_header = { .magic0 = SLA_HEADER_MAGIC0,
+ .magic1 = SLA_HEADER_MAGIC1,
+ .version = SLA_HEADER_VERSION,
+ .verifytype = SLA_HEADER_ALGORITHM_ECDSA,
+ .sigaddress = (uint32_t)&_application_end,
+ .reserved5 = SLA_HEADER_RESERVED,
+ .reserved6 = SLA_HEADER_RESERVED,
+ .reserved7 = SLA_HEADER_RESERVED };

Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c

@@ -27,16 +27,16 @@
 #include "gcr_regs.h"
 #include "mpc.h"
 
-
 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 #include "partition_max32657.h"
 
 // From linker script.
 extern uint32_t _nonsecure_start, _nonsecure_end;
 
-#define VECTOR_TABLE_START_ADDR_NS (uint32_t)(&_nonsecure_start) // Now setting the start of the vector table using a linker symbol
-#define MXC_Reset_Handler_NS (mxc_ns_call_t)*((uint32_t*)(VECTOR_TABLE_START_ADDR_NS + 4))
-#define MXC_MSP_NS *((uint32_t*)(VECTOR_TABLE_START_ADDR_NS))
+#define VECTOR_TABLE_START_ADDR_NS \
+ (uint32_t)(&_nonsecure_start) // Now setting the start of the vector table using a linker symbol
+#define MXC_Reset_Handler_NS (mxc_ns_call_t) * ((uint32_t *)(VECTOR_TABLE_START_ADDR_NS + 4))
+#define MXC_MSP_NS *((uint32_t *)(VECTOR_TABLE_START_ADDR_NS))
 #endif
 
 extern void (*const __isr_vector[])(void);
@@ -184,7 +184,6 @@ __weak void SystemInit(void)
  Board_Init();
 }
 
-
 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
 /**
  * This function is called in Secure code just before control

Libraries/PeriphDrivers/Include/MAX32657/dma.h

@@ -59,13 +59,17 @@ typedef enum {
  MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection
  MXC_DMA_REQUEST_SPIRX = MXC_S_DMA_CTRL_REQUEST_SPIRX, ///< SPI Receive DMA Request Selection
  MXC_DMA_REQUEST_UARTRX = MXC_S_DMA_CTRL_REQUEST_UARTRX, ///< UART Receive DMA Request Selection
- MXC_DMA_REQUEST_I3CRX_CONT = MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT, ///< I3C Receive Controller DMA Request Selection
- MXC_DMA_REQUEST_I3CRX_TARG = MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG, ///< I3C Receive Target DMA Request Selection
+ MXC_DMA_REQUEST_I3CRX_CONT =
+ MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT, ///< I3C Receive Controller DMA Request Selection
+ MXC_DMA_REQUEST_I3CRX_TARG =
+ MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG, ///< I3C Receive Target DMA Request Selection
  MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection
  MXC_DMA_REQUEST_SPITX = MXC_S_DMA_CTRL_REQUEST_SPITX, ///< SPI Transmit DMA Request Selection
  MXC_DMA_REQUEST_UARTTX = MXC_S_DMA_CTRL_REQUEST_UARTTX, ///< UART Transmit DMA Request Selection
- MXC_DMA_REQUEST_I3CTX_CONT = MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT, ///< I3C Transmit Controller DMA Request Selection
- MXC_DMA_REQUEST_I3CTX_TARG = MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG, ///< I3C Transmit Target DMA Request Selection
+ MXC_DMA_REQUEST_I3CTX_CONT =
+ MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT, ///< I3C Transmit Controller DMA Request Selection
+ MXC_DMA_REQUEST_I3CTX_TARG =
+ MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG, ///< I3C Transmit Target DMA Request Selection
  MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */
  MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection
 } mxc_dma_reqsel_t;

Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h

@@ -81,7 +81,8 @@ typedef enum {
  MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */
  MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */
  MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */
- MXC_SYS_PERIPH_CLOCK_DMA1 = (MXC_F_GCR_PCLKDIS1_DMA1_POS + 32), /**< Disable Secure DMA1 clock */
+ MXC_SYS_PERIPH_CLOCK_DMA1 =
+ (MXC_F_GCR_PCLKDIS1_DMA1_POS + 32), /**< Disable Secure DMA1 clock */
  MXC_SYS_PERIPH_CLOCK_WDT = (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */
 } mxc_sys_periph_clock_t;
 

Libraries/PeriphDrivers/Include/MAX32657/nspc.h

@@ -19,8 +19,6 @@
 #ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_
 #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_
 
-
-
 #include "mxc_device.h"
 #include "nspc_regs.h"
 

Libraries/PeriphDrivers/Source/DMA/dma_me30.c

@@ -39,7 +39,7 @@ int MXC_DMA_Init(mxc_dma_regs_t *dma)
  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0);
  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0);
 #if CONFIG_TRUSTED_EXECUTION_SECURE
- // DMA1 is only accessible from Secure world.
+  // DMA1 is only accessible from Secure world.
  } else if (dma == MXC_DMA1_S && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) {
  MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1);
  MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1);

Libraries/PeriphDrivers/Source/FLC/flc_reva.c

@@ -407,7 +407,8 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask)
 //******************************************************************************
 int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
 {
-#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || (TARGET_NUM != 32657) 
+#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || \
+ (TARGET_NUM != 32657)
  if ((address < MXC_INFO_MEM_BASE) ||
  (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
  return E_BAD_PARAM;
@@ -428,7 +429,8 @@ int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
 //******************************************************************************
 int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address)
 {
-#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || (TARGET_NUM != 32657) 
+#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || \
+ (TARGET_NUM != 32657)
  if ((address < MXC_INFO_MEM_BASE) ||
  (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) {
  return E_BAD_PARAM;

Libraries/PeriphDrivers/Source/TMR/tmr_revb.c

@@ -226,7 +226,8 @@ void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg)
  while (!(tmr->intfl & (MXC_F_TMR_REVB_INTFL_WRDONE_A << timerOffset))) {}
 
  tmr->cmp = (cfg->cmp_cnt << timerOffset);
-#if TARGET_NUM == 32655 || TARGET_NUM == 32657 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002
+#if TARGET_NUM == 32655 || TARGET_NUM == 32657 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || \
+ TARGET_NUM == 78002
  tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset);
 #else
  tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset);

Libraries/PeriphDrivers/Source/TZ/mpc_me30.c

@@ -39,10 +39,7 @@
 
 /**** Definitions ****/
 // Enumeration for security policy.
-typedef enum {
- MXC_MPC_STATE_SECURE = 0,
- MXC_MPC_STATE_NONSECURE = 1
-} mxc_mpc_state_t;
+typedef enum { MXC_MPC_STATE_SECURE = 0, MXC_MPC_STATE_NONSECURE = 1 } mxc_mpc_state_t;
 
 /**** Globals ****/
 
@@ -101,7 +98,7 @@ static int MXC_MPC_SetBlockSecurity(int start_addr, int end_addr, mxc_mpc_state_
 
  // Get the address range of the current MPC region.
  start_mpc_region_addr = curr_addr;
- 
+
  // NOTE: Project Owner/Developer must be aware of the memory settings for Secure and Non-Secure
  // boundaries do not share an MPC block. An MPC block can only be set to one security
  // policy (Secure or Non-Secure).
@@ -110,7 +107,8 @@ static int MXC_MPC_SetBlockSecurity(int start_addr, int end_addr, mxc_mpc_state_
  end_mpc_region_addr = phy_end_addr;
  } else {
  // -1 to get the last address of the current region.
- end_mpc_region_addr = MXC_MPC_GET_PHY_MEM_BASE(curr_mpc) + MXC_MPC_GET_PHY_MEM_SIZE(curr_mpc) - 1;
+ end_mpc_region_addr =
+ MXC_MPC_GET_PHY_MEM_BASE(curr_mpc) + MXC_MPC_GET_PHY_MEM_SIZE(curr_mpc) - 1;
  }
 
  start_block_idx = MXC_MPC_GetBlockIdx(curr_mpc, start_mpc_region_addr);
@@ -153,12 +151,14 @@ int MXC_MPC_CheckPhyBoundaries(uint32_t start_addr, uint32_t end_addr)
  phy_end_addr = end_addr & ~(1 << 28);
 
  // Check Flash Boundaries.
- if ((phy_start_addr >= MXC_PHY_FLASH_MEM_BASE) && (phy_end_addr < (MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE))) {
+ if ((phy_start_addr >= MXC_PHY_FLASH_MEM_BASE) &&
+ (phy_end_addr < (MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE))) {
  return E_NO_ERROR;
  }
 
  // Check SRAM Boundaries.
- if ((phy_start_addr >= MXC_PHY_SRAM_MEM_BASE) && (phy_end_addr < (MXC_PHY_SRAM_MEM_BASE + MXC_PHY_SRAM_MEM_SIZE))) {
+ if ((phy_start_addr >= MXC_PHY_SRAM_MEM_BASE) &&
+ (phy_end_addr < (MXC_PHY_SRAM_MEM_BASE + MXC_PHY_SRAM_MEM_SIZE))) {
  return E_NO_ERROR;
  }
 
@@ -174,17 +174,23 @@ mxc_mpc_regs_t *MXC_MPC_GetInstance(uint32_t addr)
  // by clearing bit 28 - indicates the security state of the address.
  phy_addr = addr & ~(1 << 28);
 
- if ((phy_addr >= MXC_PHY_FLASH_MEM_BASE) && (phy_addr < MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE)) {
+ if ((phy_addr >= MXC_PHY_FLASH_MEM_BASE) &&
+ (phy_addr < MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE)) {
  return MXC_MPC_FLASH;
- } else if ((phy_addr >= MXC_PHY_SRAM0_MEM_BASE) && (phy_addr < MXC_PHY_SRAM0_MEM_BASE + MXC_PHY_SRAM0_MEM_SIZE)) {
+ } else if ((phy_addr >= MXC_PHY_SRAM0_MEM_BASE) &&
+ (phy_addr < MXC_PHY_SRAM0_MEM_BASE + MXC_PHY_SRAM0_MEM_SIZE)) {
  return MXC_MPC_SRAM0;
- } else if ((phy_addr >= MXC_PHY_SRAM1_MEM_BASE) && (phy_addr < MXC_PHY_SRAM1_MEM_BASE + MXC_PHY_SRAM1_MEM_SIZE)) {
+ } else if ((phy_addr >= MXC_PHY_SRAM1_MEM_BASE) &&
+ (phy_addr < MXC_PHY_SRAM1_MEM_BASE + MXC_PHY_SRAM1_MEM_SIZE)) {
  return MXC_MPC_SRAM1;
- } else if ((phy_addr >= MXC_PHY_SRAM2_MEM_BASE) && (phy_addr < MXC_PHY_SRAM2_MEM_BASE + MXC_PHY_SRAM2_MEM_SIZE)) {
+ } else if ((phy_addr >= MXC_PHY_SRAM2_MEM_BASE) &&
+ (phy_addr < MXC_PHY_SRAM2_MEM_BASE + MXC_PHY_SRAM2_MEM_SIZE)) {
  return MXC_MPC_SRAM2;
- } else if ((phy_addr >= MXC_PHY_SRAM3_MEM_BASE) && (phy_addr < MXC_PHY_SRAM3_MEM_BASE + MXC_PHY_SRAM3_MEM_SIZE)) {
+ } else if ((phy_addr >= MXC_PHY_SRAM3_MEM_BASE) &&
+ (phy_addr < MXC_PHY_SRAM3_MEM_BASE + MXC_PHY_SRAM3_MEM_SIZE)) {
  return MXC_MPC_SRAM3;
- } else if ((phy_addr >= MXC_PHY_SRAM4_MEM_BASE) && (phy_addr < MXC_PHY_SRAM4_MEM_BASE + MXC_PHY_SRAM4_MEM_SIZE)) {
+ } else if ((phy_addr >= MXC_PHY_SRAM4_MEM_BASE) &&
+ (phy_addr < MXC_PHY_SRAM4_MEM_BASE + MXC_PHY_SRAM4_MEM_SIZE)) {
  return MXC_MPC_SRAM4;
  } else {
  // Addresses are located outside of memory spaces that don't have an
@@ -215,7 +221,7 @@ int MXC_MPC_GetBlockIdx(mxc_mpc_regs_t *mpc, uint32_t addr)
  block_size = 1 << ((mpc->blk_cfg & MXC_F_MPC_BLK_CFG_SIZE) + 5);
 
  // Clear bit 28 (Security State of Region) to get the physical memory address.
- physical_addr &= ~(1<<28);
+ physical_addr &= ~(1 << 28);
 
  base = addr - start_mpc_region_addr;
  block = base / block_size;

Libraries/PeriphDrivers/Source/TZ/spc_me30.c

@@ -163,15 +163,17 @@ void MXC_SPC_PPC_ClearFlags(uint32_t flags)
 }
 
 // TODO(SW): This requires testing. ICODE
-void MXC_SPC_SetCode_NSC(bool isNSC) {
+void MXC_SPC_SetCode_NSC(bool isNSC)
+{
  if (isNSC) {
  MXC_SPC->nscidau |= MXC_F_SPC_NSCIDAU_CODE;
  } else {
  MXC_SPC->nscidau &= ~MXC_F_SPC_NSCIDAU_CODE;
  }
 }
 
-void MXC_SPC_SetSRAM_NSC(bool isNSC) {
+void MXC_SPC_SetSRAM_NSC(bool isNSC)
+{
  if (isNSC) {
  MXC_SPC->nscidau |= MXC_F_SPC_NSCIDAU_SRAM;
  } else {

Libraries/PeriphDrivers/Source/UART/uart_revb.c

@@ -914,7 +914,7 @@ void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned
  if (dma_instance == MXC_DMA0) {
  MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler);
 #if CONFIG_TRUSTED_EXECUTION_SECURE
- // Only secure code has access to Secure DMA (DMA1).
+  // Only secure code has access to Secure DMA (DMA1).
  } else if (dma_instance == MXC_DMA1) {
  MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler);
 #endif // CONFIG_TRUSTED_EXECUTION_SECURE