Fix PART_ID register

analogdevicesinc · Sep 24, 2024 · 56afb82 · 56afb82
1 parent d35c479
commit 56afb82
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Showing 4 changed files with 40 additions and 24 deletions.
diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_one_regs.h
@@ -7,9 +7,7 @@
 
 /******************************************************************************
  *
- * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
- * Analog Devices, Inc.),
- * Copyright (C) 2023-2024 Analog Devices, Inc.
+ * Copyright (C) 2024 Analog Devices, Inc.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -563,7 +561,10 @@ extern "C" {
  * @{
  */
 #define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS           0 /**< PART_ID_REV_ID Position */
-#define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID               ((uint32_t)(0x7UL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
+#define MXC_F_AFE_ADC_ONE_PART_ID_REV_ID               ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ONE_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
+
+#define MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS          5 /**< PART_ID_ADC_SEL Position */
+#define MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL              ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ONE_PART_ID_ADC_SEL_POS)) /**< PART_ID_ADC_SEL Mask */
 
 /**@} end of group AFE_ADC_ONE_PART_ID_Register */
 

diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h
@@ -7,9 +7,7 @@
 
 /******************************************************************************
  *
- * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
- * Analog Devices, Inc.),
- * Copyright (C) 2023-2024 Analog Devices, Inc.
+ * Copyright (C) 2024 Analog Devices, Inc.
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -93,7 +91,6 @@ extern "C" {
 #define MXC_R_AFE_ADC_ZERO_PGA             ((uint32_t)0x000E0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0xE0001</tt> */
 #define MXC_R_AFE_ADC_ZERO_WAIT_EXT        ((uint32_t)0x000F0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0xF0001</tt> */
 #define MXC_R_AFE_ADC_ZERO_WAIT_START      ((uint32_t)0x00100001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x100001</tt> */
-#define MXC_R_AFE_ADC_ZERO_PART_ID         ((uint32_t)0x00110003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x110003</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYSC_SEL        ((uint32_t)0x00120003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x120003</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYS_OFF_A       ((uint32_t)0x00130003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x130003</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYS_OFF_B       ((uint32_t)0x00140003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x140003</tt> */
@@ -194,6 +191,7 @@ extern "C" {
 #define MXC_R_AFE_ADC_ZERO_ANA_TRIM        ((uint32_t)0x00790002UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x790002</tt> */
 #define MXC_R_AFE_ADC_ZERO_SYS_CTRL        ((uint32_t)0x007A0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x7A0001</tt> */
 #define MXC_R_AFE_ADC_ZERO_TS_CTRL         ((uint32_t)0x007C0001UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x7C0001</tt> */
+#define MXC_R_AFE_ADC_ZERO_PART_ID         ((uint32_t)0x00910003UL) /**< Offset from AFE_ADC_ZERO Base Address: <tt> 0x910003</tt> */
 /**@} end of group afe_adc_zero_registers */
 
 /**
@@ -556,17 +554,6 @@ extern "C" {
 
 /**@} end of group AFE_ADC_ZERO_WAIT_EXT_Register */
 
-/**
- * @ingroup  afe_adc_zero_registers
- * @defgroup AFE_ADC_ZERO_PART_ID AFE_ADC_ZERO_PART_ID
- * @brief    Silicon Revision ID
- * @{
- */
-#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS          0 /**< PART_ID_REV_ID Position */
-#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID              ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
-
-/**@} end of group AFE_ADC_ZERO_PART_ID_Register */
-
 /**
  * @ingroup  afe_adc_zero_registers
  * @defgroup AFE_ADC_ZERO_SYSC_SEL AFE_ADC_ZERO_SYSC_SEL
@@ -2041,6 +2028,20 @@ extern "C" {
 
 /**@} end of group AFE_ADC_ZERO_TS_CTRL_Register */
 
+/**
+ * @ingroup  afe_adc_zero_registers
+ * @defgroup AFE_ADC_ZERO_PART_ID AFE_ADC_ZERO_PART_ID
+ * @brief    Silicon Revision ID
+ * @{
+ */
+#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS          0 /**< PART_ID_REV_ID Position */
+#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID              ((uint32_t)(0x1FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */
+
+#define MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL_POS         5 /**< PART_ID_ADC_SEL Position */
+#define MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL             ((uint32_t)(0x1UL << MXC_F_AFE_ADC_ZERO_PART_ID_ADC_SEL_POS)) /**< PART_ID_ADC_SEL Mask */
+
+/**@} end of group AFE_ADC_ZERO_PART_ID_Register */
+
 #ifdef __cplusplus
 }
 #endif

diff --git a/Libraries/PeriphDrivers/Source/AFE/afe_adc_one_reva.svd b/Libraries/PeriphDrivers/Source/AFE/afe_adc_one_reva.svd
@@ -700,9 +700,16 @@
         <fields>
           <field>
             <name>REV_ID</name>
-            <description>Description not included</description>
+            <description>Revision ID.</description>
             <bitOffset>0</bitOffset>
-            <bitWidth>3</bitWidth>
+            <bitWidth>5</bitWidth>
+            <access>read-only</access>
+          </field>
+          <field>
+            <name>ADC_SEL</name>
+            <description>ADC Selected.</description>
+            <bitOffset>5</bitOffset>
+            <bitWidth>1</bitWidth>
             <access>read-only</access>
           </field>
         </fields>

diff --git a/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd b/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd
@@ -696,13 +696,20 @@
       <register>
         <name>PART_ID</name>
         <description>Silicon Revision ID</description>
-        <addressOffset>0x00110003</addressOffset>
+        <addressOffset>0x00910003</addressOffset>
         <fields>
           <field>
             <name>REV_ID</name>
-            <description>Description not included</description>
+            <description>Revision ID.</description>
             <bitOffset>0</bitOffset>
-            <bitWidth>6</bitWidth>
+            <bitWidth>5</bitWidth>
+            <access>read-only</access>
+          </field>
+          <field>
+            <name>ADC_SEL</name>
+            <description>ADC Selected.</description>
+            <bitOffset>5</bitOffset>
+            <bitWidth>1</bitWidth>
             <access>read-only</access>
           </field>
         </fields>