Merge pull request #428 from paulusmack/ecpix-5

ECPIX-5 support

Makefile

@@ -164,7 +164,7 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex
 #MEMORY_SIZE=393216
 #RAM_INIT_FILE=micropython/firmware.hex
 
-FPGA_TARGET ?= ORANGE-CRAB-0.21
+FPGA_TARGET ?= ECPIX-5
 
 clkgen=fpga/clk_gen_ecp5.vhd
 toplevel=fpga/top-generic.vhdl
@@ -199,7 +199,7 @@ DFU_PRODUCT=5af0
 ECP_FLASH_OFFSET=0x80000
 toplevel=fpga/top-orangecrab0.2.vhdl
 litedram_target=orangecrab-85-0.2
-soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
+soc_extra_v += litesdcard/generated/lattice.48e6/litesdcard_core.v
 dmi_dtm=dmi_dtm_ecp5.vhdl
 endif
 
@@ -215,6 +215,23 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
 OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
 endif
 
+# ECPIX-5
+ifeq ($(FPGA_TARGET), ECPIX-5)
+RESET_LOW=true
+CLK_INPUT=100000000
+CLK_FREQUENCY=50000000
+LPF=constraints/ecpix-5.lpf
+PACKAGE=CABGA554
+NEXTPNR_FLAGS=--um5g-85k --speed 8 --freq 50 --timing-allow-fail --ignore-loops
+OPENOCD_JTAG_CONFIG=openocd/ecpix-5.cfg
+OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
+toplevel=fpga/top-ecpix5.vhdl
+litedram_target=ecpix-5
+soc_extra_v += litesdcard/generated/lattice.50e6/litesdcard_core.v
+soc_extra_v += liteeth/generated/ecpix-5/liteeth_core.v
+dmi_dtm=dmi_dtm_ecp5.vhdl
+endif
+
 ifneq ($(litedram_target),)
 soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
 	litedram/generated/$(litedram_target)/litedram-initmem.vhdl