awesome-opensource-hardware

A curated list of awesome open source hardware tools.

• Categorized
• Alphabetical (per category)
• Requirements
  • link should be to source code repository
  • open source projects only
  • working projects only (not WIP/rusty)
• One tag line sentence per project.

Accelerators

• aes
  • Symmetric block cipher AES (Advanced Encryption Standard)
• ara
  • Vector Unit, compatible with the RISC-V Vector Extension
• FFTGenerator
  • MMIO-Based FFT Generator
• fpu
  • Synthesizable ieee 754 floating point library in verilog
• gemmini
  • Berkeley Spatial Array Generator
• gplgpu
  • GPL v3 2D/3D graphics engine in verilog
• core_jpeg
  • High throughput JPEG decoder in Verilog for FPGA
• h265-encoder-rtl
  • H.265 Video Encoder IP Core
• nvdla
  • NVIDIA Deep Learning Accelerator (NVDLA)
• NyuziProcessor
  • GPGPU microprocessor architecture
• openofdm
  • 802.11 OFDM PHY decoder
• sha3
  • Berkeley SHAR3 ROCC Accelerator
• tvm-vta
  • Opwn, modular, deep learning accelerator
• VeriGOOD-ML
  • Verilog Generator, Optimized for Designs for Machine Learning
• VeriGPU
  • OpenSource GPU, loosely based on RISC-V ISA
• verilog-lfsr
  • Parametrizable combinatorial parallel LFSR/CRC module
• vortex
  • Full-system RISCV-based GPGPU processor

Analog

• AMS_KGD
  • Repository for Known Good Analog Designs (KGDs)
• open-pmic
  • Current mode buck converter on the SKY130 PDK
• Analog Basic Blocks/LDO
  • Repo that has designs with the following: OTA, BandGap and LDO design on Skywaters 130nm.

Boards

• parallella-hw
  • Parallella board design files

Connectivity

• aib
  • Advanced Interface Bus (AIB) die to die hardware
• aib-protocols
  • Advanced Interface Bus (AIB) Protocol IP
• axi
  • AXI SystemVerilog synthesizable IP
• axi4_aib_bridge
  • AXI4/AIB Bridge RTL
• core_ddr3_controller
  • DDR3 memory controller in Verilog for various FPGAs
• hdmi
  • Send video/audio over HDMI on an FPGA
• i2c
  • Fully featured implementation of Inter-IC (I2C) bus master
• litedram
  • Small footprint and configurable DRAM (litex)
• liteeth
  • Small footprint and configurable Ethernet core
• litescope
  • Small footprint and configurable embedded FPGA logic analyzer
• litepice
  • Small footprint and configurable PCIe core
• OpenSERDES
  • Digitally synthesizable architecture for SerDes using Skywater130
• ravenoc
  • Configurable HDL NoC (Network-On-Chip)
• tnoc
  • Network on Chip Implementation written in SytemVerilog
• verilog-axis
  • Verilog AXI stream components for FPGA implementation
• verilog-ethernet
  • Verilog Ethernet components for FPGA implementation
• verilog-i2c
  • Verilog I2C interface for FPGA implementation
• verilog-uart
  • Verilog UART
• verilog-pcie
  • Verilog PCI express components
• verilog-wishbone
  • Verilog wishbone components
• wav-d2d-hw
  • 8lane Wlink with D2D and a single AXI Target/Initiator
• wav-lpddr-hw
  • DDR (WDDR) Physical interface (PHY) Hardware
• wav-slink-hw
  • Chiplet link
• wav-wlink-hw
  • Chiplet link

CPU cores

• a2i
  • A2I POWER processor core RTL (VHDL)
• black-parrot
  • Linux-capable RISC-V multicore
• Cores-SweRV
  • SweRV EH1 RISC-Vcore
• Cores-SweRV-EL2
  • SweRV EL2 RISC-V Core
• core-v-verif
  • Functional verification project for the CORE-V family of RISC-V cores
• cva6
  • Linux capable RISC-V CPU
• cv32e40p
  • RV32IMFCX RISC-V 4-stage RISC-V CPU
• ibex
  • Small 32 bit RISC-V CPU core
• HuanCun
  • Open-source high-performance non-blocking cache
• microwatt
  • Open POWER ISA softcore written in VHDL 2008
• neorv32
  • Customizable and highly extensible MCU-class 32-bit RISC-V (VHDL)
• OpenXiangShan
  • Open-source high-performance RISC-V processor
• picorv32
  • Size-Optimized RISC-V CPU
• rocket-chip
  • Linux capable RISC-V Rocket Chip Generator
• serv
  • SErial RISC-V CPU
• snitch
  • Lean but mean RISC-V system

FPGAs

• FABulous
  • Fabric generator and CAD tools
• fabric_team
  • ucb-cs250 FPGA class project
• OpenFPGA
  • FPGA IP Generator
• prga
  • Open-source FPGA research and prototyping framework

Libraries

• basic_verilog
  • Library of SystemVerilog components
• common_cells
  • Library of SystemVerilog components
• hdl
  • Library of Analog Deveices specific components
• oh
  • Library of Verilog components
• basejump_stl
  • Library of SystemVerilog components

Memory

• core_axi_cache
  • 128KB AXI cache (32-bit in, 256-bit out)

Packaging

• bsg_packaging
  • Open-Source Hardware Accelerator Packages and Sockets

Retro

• VerilogBoy
  • Game Boy compatible machine with Verilog

Systems

• Beagle_SDR_GPS
  • KiwiSDR: BeagleBone web-accessible GPS/SDR
• bsg_manycore
  • Tile based architecture designed for computing efficiency, scalability
• esp
  • Heterogeneous SoC architecture and IP design platform
• hero
  • FPGA-based research platform for heterogeneous design
• litex
  • SoC builder framework
• openFASOC
  • Open Source FASOC generators
• openpiton
  • General purpose, multithreaded manycore processor
• opentitan
  • Open source silicon root of trust
• openwifi-hw
  • IEEE 802.11 WiFi baseband FPGA (chip) design
• pulp
  • Multicore RISC-V based SoC
• pulpissimo
  • Single core RISC-V based SoC