austindriggs / simple-cpu-design Public

Design of a Simple CPU using the DE10-Lite FPGA from Intel and Quartus Prime

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
db		db
docs		docs
incremental_db		incremental_db
output_files		output_files
simulation/qsim		simulation/qsim
ControlUnit.vhd		ControlUnit.vhd
ControlUnit.vhd.bak		ControlUnit.vhd.bak
ProgramCounter.vhd		ProgramCounter.vhd
ProgramCounter.vhd.bak		ProgramCounter.vhd.bak
README.md		README.md
SimpleCPU_Template.vhd		SimpleCPU_Template.vhd
SimpleCPU_Template.vhd.bak		SimpleCPU_Template.vhd.bak
TwoToOneMux.vhd		TwoToOneMux.vhd
TwoToOneMux.vhd.bak		TwoToOneMux.vhd.bak
Waveform.vwf		Waveform.vwf
alu.vhd		alu.vhd
alu.vhd.bak		alu.vhd.bak
cpe271-final-project.qpf		cpe271-final-project.qpf
cpe271-final-project.qsf		cpe271-final-project.qsf
cpe271-final-project.qws		cpe271-final-project.qws
cpu.vhd		cpu.vhd
cpu.vhd.bak		cpu.vhd.bak
memory_8_by_32.vhd		memory_8_by_32.vhd
memory_8_by_32.vhd.bak		memory_8_by_32.vhd.bak
reg.vhd		reg.vhd
reg.vhd.bak		reg.vhd.bak
sevenseg.vhd		sevenseg.vhd
sevenseg.vhd.bak		sevenseg.vhd.bak