Merge pull request #118 from albrecht-flo/xpsr_register

Fix xpsr register issues between QEmu and OpenOCD targets

avatar2/archs/arm.py

@@ -1,5 +1,3 @@
-# from capstone import CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, CS_MODE_BIG_ENDIAN
-
 from capstone import *
 from keystone.keystone_const import *
 from unicorn import *
@@ -9,17 +7,17 @@
 
 from avatar2.installer.config import QEMU, PANDA, OPENOCD, GDB_MULTI
 
+
 class ARM(Architecture):
 
  get_qemu_executable = Architecture.resolve(QEMU)
  get_panda_executable = Architecture.resolve(PANDA)
- get_gdb_executable  = Architecture.resolve(GDB_MULTI)
+ get_gdb_executable = Architecture.resolve(GDB_MULTI)
  get_oocd_executable = Architecture.resolve(OPENOCD)
 
-
-
  qemu_name = 'arm'
  gdb_name = 'arm'
+ # Based on gdb profile
  registers = {'r0': 0, 'r1': 1, 'r2': 2, 'r3': 3, 'r4': 4, 'r5': 5, 'r6': 6,
  'r7': 7, 'r8': 8, 'r9': 9, 'r10': 10, 'r11': 11, 'r12': 12, 'ip': 12,
  'sp': 13, 'lr': 14, 'pc': 15, 'cpsr': 25,
@@ -40,6 +38,7 @@ class ARM(Architecture):
  unicorn_arch = UC_ARCH_ARM
  unicorn_mode = UC_MODE_ARM
 
+
 class ARM_CORTEX_M3(ARM):
  cpu_model = 'cortex-m3'
  qemu_name = 'arm'
@@ -53,11 +52,12 @@ class ARM_CORTEX_M3(ARM):
  unicorn_arch = UC_ARCH_ARM
  unicorn_mode = UC_MODE_LITTLE_ENDIAN | UC_MODE_THUMB
  sr_name = 'xpsr'
-
+ # The xpsr register has different register numbers across QEmu and OpenOCD, so we make sure to read/write it only by name
+ special_registers = {'xpsr': {'gdb_expression': "$xpsr", 'format': "{:d}"}}
 
  @staticmethod
  def register_write_cb(avatar, *args, **kwargs):
- 
+
  if isinstance(kwargs['watched_target'],
  avatar2.targets.qemu_target.QemuTarget):
  qemu = kwargs['watched_target']
@@ -72,10 +72,10 @@ def register_write_cb(avatar, *args, **kwargs):
 
  if args[0] == 'pc' or args[0] == 'cpsr':
  cpsr = qemu.protocols.registers.read_register('cpsr')
- if cpsr & 1<< shiftval:
+ if cpsr & 1 << shiftval:
  return
  else:
- cpsr |= 1<<shiftval
+ cpsr |= 1 << shiftval
  qemu.protocols.registers.write_register('cpsr', cpsr)
 
  @staticmethod
@@ -84,6 +84,8 @@ def init(avatar):
  ARM_CORTEX_M3.register_write_cb)
 
  pass
+
+
 ARMV7M = ARM_CORTEX_M3
 
 

avatar2/avatar2.py

@@ -383,6 +383,7 @@ def transfer_state(self, from_target, to_target, sync_regs=True, synced_ranges=[
  # Sync the registers!
  for r in regs:
  val = from_target.read_register(r)
+ self.log.debug("Synchronizing register %6s (%s) " % (r, val))
  to_target.write_register(r, val)
  self.log.info("Synchronized Registers")
 

generate_dockerfile.py

@@ -5,7 +5,7 @@
 
 DESCRIPTION="Script to build avatar2 core and its endpoints using Docker."
 USAGE=""" generate_dockerfile.py [options]
-Exemple: 
+Example: 
  ./generate_dockerfile.py \\
  --endpoint_list avatar-qemu panda \\
  --qemu_targets arm-softmmu mips-softmmu