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fix(riscv): add low order bits to faulting address #332

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fix(riscv): add low order bits to faulting address

fix(riscv): add low order bits to faulting address #332

Workflow file for this run

.github/workflows/build-arm.yaml at 9bfb820
name: Arm Build
on:
push:
branches: [ main ]
pull_request:
workflow_dispatch:
jobs:
build-arm:
runs-on: ubuntu-latest
container: baoproject/bao:latest
strategy:
matrix:
platform: [
"fvp-a",
"fvp-a-aarch32",
"fvp-r",
"fvp-r-aarch32"
]
gic: [
"GICV2",
"GICV3",
]
cross_compile: [
"",
"CROSS_COMPILE=clang",
]
steps:
- uses: actions/checkout@v4
with:
submodules: recursive
- run: make PLATFORM=${{ matrix.platform }} GIC_VERSION=${{ matrix.gic }} \
CONFIG=null ${{ matrix.cross_compile }}