feat(riscv/aclint): make platform aclint support compile opt

Add the IPIC option on QEMU platform to select
ACLINT or SBI as the interrupt controller for IPIs

Signed-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>

Makefile

@@ -143,6 +143,8 @@ gens+=$(config_def_generator) $(config_defs)
 inc_dirs+=$(config_build_dir)
 
 platform_def_generator_src:=$(scripts_dir)/platform_defs_gen.c
+platform_arch_def_generator_src:=$(wildcard $(scripts_dir)/arch/$(ARCH)/platform_defs_gen.c)
+platform_def_generator_src+=$(platform_arch_def_generator_src)
 platform_def_generator:=$(scripts_build_dir)/platform_defs_gen
 platform_defs:=$(platform_build_dir)/platform_defs_gen.h
 platform_description:=$(platform_dir)/$(platform_description)

scripts/arch/riscv/platform_defs_gen.c

@@ -0,0 +1,15 @@
+/**
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) Bao Project and Contributors. All rights reserved
+ */
+
+#include <stdio.h>
+#include <platform.h>
+
+void arch_platform_defs() {
+
+    if (platform.arch.aclint_sswi.base != 0) {
+        printf("#define ACLINT_SSWI 1\n");
+    }
+
+}

scripts/platform_defs_gen.c

@@ -6,7 +6,9 @@
 #include <stdio.h>
 #include <platform.h>
 
-extern void arch_platform_defs();
+__attribute__((weak)) void arch_platform_defs(void){
+    return;
+}
 
 int main() {
 
@@ -15,6 +17,7 @@ int main() {
     if (platform.cpu_master_fixed) {
         printf("#define CPU_MASTER_FIXED (%ld)\n", platform.cpu_master);
     }
-
+    // Call arch specific platform defines generator
+    arch_platform_defs();
     return 0;
 }

src/arch/riscv/arch.mk

@@ -18,9 +18,6 @@ irqc_arch_dir=$(cpu_arch_dir)/irqc/$(IRQC_DIR)
 src_dirs+=$(irqc_arch_dir)
 
 arch-cppflags+=-DIRQC=$(IRQC)
-ifeq ($(ACLINT_PRESENT), 1)
-arch-cppflags+=-DACLINT_PRESENT
-endif
 arch-cflags = -mcmodel=medany -march=rv64g -mstrict-align
 arch-asflags =
 arch-ldflags = 

src/arch/riscv/inc/arch/interrupts.h

@@ -12,6 +12,8 @@
 #define PLIC  (1)
 #define APLIC (2)
 
+#define ACLINT_PRESENT() DEFINED(ACLINT_SSWI)
+
 /**
  * In riscv, the ipi (software interrupt) and timer interrupts dont actually
  * have an ID as their are treated differently from external interrupts

src/arch/riscv/interrupts.c

@@ -20,7 +20,7 @@ void interrupts_arch_init()
 {
     if (cpu()->id  == CPU_MASTER) {  
         irqc_init();
-        if(DEFINED(ACLINT_PRESENT)){
+        if(ACLINT_PRESENT()){
             aclint_init();
         }
     }
@@ -38,7 +38,7 @@ void interrupts_arch_init()
 
 void interrupts_arch_ipi_send(cpuid_t target_cpu, irqid_t ipi_id)
 {
-    if (DEFINED(ACLINT_PRESENT)) {
+    if (ACLINT_PRESENT()) {
         aclint_send_ipi(target_cpu);
     } else {
         sbi_send_ipi(1ULL << target_cpu, 0);

src/platform/qemu-riscv64-virt/inc/plat/platform.h

@@ -10,4 +10,7 @@
 
 #define CPU_EXT_SSTC    1
 
+#define IPIC_SBI (1)
+#define IPIC_ACLINT (2)
+
 #endif

src/platform/qemu-riscv64-virt/platform.mk

@@ -7,12 +7,14 @@ ARCH:=riscv
 CPU:=
 # Interrupt controller definition
 IRQC:=PLIC
+# Core IPIs controller
+IPIC:=IPIC_ACLINT
 
 drivers := sbi_uart
 
 platform_description:=virt_desc.c
 
-platform-cppflags =
+platform-cppflags =-DIPIC=$(IPIC)
 platform-cflags = 
 platform-asflags =
 platform-ldflags =

src/platform/qemu-riscv64-virt/virt_desc.c

@@ -26,8 +26,14 @@ struct platform platform = {
         #else 
         #error "unknown IRQC type " IRQC
         #endif
-        // Disable ACLINT by default
-        .aclint_sswi.base = 0
+
+        #if (IPIC == IPIC_SBI)
+        .aclint_sswi.base = 0,
+        #elif (IPIC == IPIC_ACLINT)
+        .aclint_sswi.base = 0x2f00000,
+        #else 
+        #error "unknown IPIC type " IPIC
+        #endif
     }
 
 };