Another way of writing primary outputs in Verilog. #384
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name: Build Windows | |
on: | |
push: | |
pull_request: | |
jobs: | |
build-windows: | |
runs-on: windows-2019 | |
steps: | |
- name: Git Checkout | |
uses: actions/checkout@v2 | |
with: | |
submodules: recursive | |
- name: Process project files to compile on Github Actions | |
run: | | |
sed -i 's#ABC_USE_PTHREADS\"#ABC_DONT_USE_PTHREADS\" /D \"_ALLOW_KEYWORD_MACROS=1\"#g' *.dsp | |
awk 'BEGIN { del=0; } /# Begin Group "uap"/ { del=1; } /# End Group/ { if( del > 0 ) {del=0; next;} } del==0 {print;} ' abclib.dsp > tmp.dsp | |
copy tmp.dsp abclib.dsp | |
del tmp.dsp | |
unix2dos *.dsp | |
- name: Prepare MSVC | |
uses: bus1/cabuild/action/msdevshell@v1 | |
with: | |
architecture: x86 | |
- name: Upgrade project files to latest Visual Studio, ignoring upgrade errors, and build | |
run: | | |
devenv abcspace.dsw /upgrade ; if (-not $? ) { cat UpgradeLog.htm } | |
msbuild abcspace.sln /m /nologo /p:Configuration=Release /p:PlatformTarget=x86 | |
- name: Test Executable | |
run: | | |
_TEST\abc.exe -c "r i10.aig; b; ps; b; rw -l; rw -lz; b; rw -lz; b; ps; cec" | |
- name: Stage Executable | |
run: | | |
mkdir staging | |
copy _TEST/abc.exe staging/ | |
copy UpgradeLog.htm staging/ | |
- name: Upload pacakge artifact | |
uses: actions/upload-artifact@v1 | |
with: | |
name: package | |
path: staging/ |