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added ctrl-c handling
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billmcspadden-riscv committed Oct 9, 2024
1 parent 0ed8863 commit 31d06fd
Showing 1 changed file with 46 additions and 9 deletions.
55 changes: 46 additions & 9 deletions bin/run_tests.py
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,7 @@
import glob # needed for file list gathering useing wildcards
import re # regular expression
import sys # needed for command line arguments
import signal # needed for signal handling (cntl-C especially)
import getopt # needed for command line arguments
import collections # needed for dequeues
import subprocess # needed for subprocesses where stdout is needed
Expand All @@ -54,6 +55,8 @@
# Data structure for sim command line arguments
# TODO: make the key a regex
sim_test_command_line_switch_dict = { }
sim_test_command_line_switch_dict = { }
sim_test_command_line_switch = { }
my_ignore_test_tuple = []

# Allowed command line options
Expand Down Expand Up @@ -149,6 +152,25 @@ def TRACE(text = "") :
# Print Levels:
# ====================================

# ====================================
# Subprocess support functions
def subproc(cmd) :
try:
debug_print("subproc: cmd: " + cmd)
# ret = os.system(cmd)
subprocess.check_call(cmd, shell = True)
except KeyboardInterrupt as e:
debug_print("interrupted: subproc: cmd: " + cmd)
sys.exit(1)
except:
debug_print("subproc: cmd: " + cmd)
return 1
else:
return 0

# Subprocess support functions
# ====================================

# ====================================
# Support for command line options
def print_usage(invocation) :
Expand Down Expand Up @@ -402,17 +424,24 @@ def ignore_test(testname) :
# Functions for determining file types
# ====================================

def signal_handler(sig, frame):
degug_print("entering signal_handler() for signal ", sig)
sys.exit(1)


# Function prototypes
# ===========================================================================79

# ===========================================================================79
# Start of execution....

process_command_line_args(opts)
#signal.signal(signal.SIGINT, signal_handler)

debug_print("starting...")
debug_print("abspath to this script: " + os.path.abspath(sys.argv[0]))
debug_print("opts: " + str(opts))

process_command_line_args(opts)

# ====================================
# Implicit overrides of program varaibles
Expand Down Expand Up @@ -478,7 +507,8 @@ def ignore_test(testname) :

if clean_build :
cmd = "make ARCH=RV32 clean"
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val != 0 :
fatal_print("non-zero exit value from command: '" + cmd + "'")
else :
Expand All @@ -488,7 +518,8 @@ def ignore_test(testname) :

if clean_build :
cmd = "make ARCH=RV32 clean"
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val != 0 :
fatal_print("non-zero exit value from command: '" + cmd + "'")
sys.exit(1)
Expand All @@ -502,7 +533,8 @@ def ignore_test(testname) :
if run_csim :
if run_32bit_tests :
cmd = "make ARCH=RV32 " + MAKE_SAILCOV + " c_emulator/riscv_sim_RV32"
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val == 0 :
green("Building 32-bit RISCV C emulator", "ok")
else :
Expand Down Expand Up @@ -532,7 +564,8 @@ def ignore_test(testname) :

cmd = "timeout 5 " + RISCVDIR + "/c_emulator/riscv_sim_RV32" + run_sailcov + " " + sim_switch + " " + test + " > " + outfile + " 2>&1 && grep -q SUCCESS " + outfile
debug_print("cmd: '" + cmd + "'")
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val == 0 :
green("C-32 " + os.path.basename(test), "ok")
else :
Expand All @@ -544,7 +577,8 @@ def ignore_test(testname) :

if clean_build :
cmd = "make ARCH=RV64 clean"
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val != 0 :
fatal_print("non-zero exit value from command: '" + cmd + "'")
else :
Expand All @@ -556,7 +590,8 @@ def ignore_test(testname) :

if clean_build :
cmd = "make ARCH=RV64 clean"
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val != 0 :
fatal_print("non-zero exit value from command: '" + cmd + "'")
else :
Expand All @@ -568,7 +603,8 @@ def ignore_test(testname) :
if run_csim :
if run_64bit_tests :
cmd = "make ARCH=RV64 " + MAKE_SAILCOV + " c_emulator/riscv_sim_RV64"
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val == 0 :
green("Building 64-bit RISCV C emulator", "ok")
else :
Expand Down Expand Up @@ -598,7 +634,8 @@ def ignore_test(testname) :
run_sailcov = ""

cmd = "timeout 5 " + RISCVDIR + "/c_emulator/riscv_sim_RV64" + run_sailcov + " " + sim_switch + " " + test + " > " + outfile + " 2>&1 && grep -q SUCCESS " + outfile
ret_val = os.system(cmd)
ret_val = subproc(cmd)
# ret_val = os.system(cmd)
if ret_val == 0 :
green("C-64 " + os.path.basename(test), "ok")
else :
Expand Down

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