debug: Fix nonexistent trigger registers trap handle in entry.S

billmcspadden-riscv · Apr 17, 2024 · 7f454c3 · 7f454c3
1 parent 6b1d737
commit 7f454c3
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/debug/programs/entry.S b/debug/programs/entry.S
@@ -84,8 +84,9 @@ handle_reset:
   beq   t0, t1, 1b
 .p2align 2
 2:
-  # Restore mtvec
+  # Restore mtvec and mstatus
   csrw mtvec, t2
+  csrwi mstatus, 0
 
 #ifdef MULTICORE
   csrr  t0, CSR_MHARTID