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revert to vanilla
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mean committed Nov 21, 2024
1 parent 7a8820e commit 3ad0283
Showing 1 changed file with 4 additions and 5 deletions.
9 changes: 4 additions & 5 deletions src/target/riscv_debug.c
Original file line number Diff line number Diff line change
Expand Up @@ -1013,11 +1013,10 @@ static void riscv_halt_resume(target_s *target, const bool step)
uint32_t stepping_config = 0U;
if (!riscv_csr_read(hart, RV_DCSR | RV_CSR_FORCE_32_BIT, &stepping_config))
return;
if (step) {
stepping_config |= RV_DCSR_STEP;
stepping_config &= ~RV_DCSR_STEPIE; // disable interrupt during single step
} else {
stepping_config &= ~RV_DCSR_STEP;
if (step)
stepping_config |= RV_DCSR_STEP | RV_DCSR_STEPIE;
else {
stepping_config &= ~(RV_DCSR_STEP | RV_DCSR_STEPIE);
stepping_config |= RV_DCSR_EBREAK_MACHINE;
}
if (!riscv_csr_write(hart, RV_DCSR | RV_CSR_FORCE_32_BIT, &stepping_config))
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