Feature: WCH RISC-V support #1399

perigoso · 2023-02-23T15:46:34Z

Detailed description

Support support for WCH RISC-V family of MCUs

WCH uses a custom DTM (Debug Transport Module) for their RISC-V MCUs, RVSWD a 2 wire SWD "like" protocol (not SWD), and a SDI 1 wire protocol

RVSWD is currently not publlicly documented, part of this implementation is the reverse engineering of the protocol, resulting documentation will be hosted here

Sigrok protocol decoder for RVSWD here

SDI documentation has been recently published, but implementation of will probably come as a separate PR
The only SDI MCU at the moment is the CH32V003, all other WCH RISC-V MCUs use RVSWD

As part of the process support for the WCH-Link debug probe by WCH is also implemented, it's a naive implementation based on a rough reverse engineer of the protocol, which too is not publicly documented

This PR might be broken down in the future

As this PR is built on top of feature/esp32-c3-support it might be hard to read, try this diff (feature/esp32-c3-support <- feature/wch-support)

Discord thread

Your checklist for this pull request

I've read the Code of Conduct
I've read the guidelines for contributing to this repository
It builds for hardware native (make PROBE_HOST=native)
It builds as BMDA (make PROBE_HOST=hosted)
I've tested it to the best of my ability
My commit messages provide a useful short description of what the commits do

Closing issues

This PR is targeted at v2.0 milestone

Depends on #292 and feature/esp32-c3-support

Closes #1576

dragonmux · 2023-10-31T06:08:18Z

Please rebase this on feature/esp32-c3-support when you get a chance.

koendv · 2023-12-13T05:57:58Z

This is a PR I would not mind testing, But it needs rebasing.

perigoso · 2023-12-13T14:41:57Z

This is a PR I would not mind testing, But it needs rebasing.

You can test as is, it should compile and work (and would be welcome!), that said it does need rebasing, but I'm tight on free time for a bit. Maybe at the begining of the new year.

perigoso · 2023-12-15T18:22:19Z

@koendv Got some time and rebased this on main. Unfortunately the last commit is extremely experimental and not in a state for a clean rebase, so I just reverted the files to the state on the original PR, meaning it reverts some probably important changes on the current main, beware! It should work for scan of CH32 Risc-V chips with the WCH-LinkE, I just tested.

koendv · 2023-12-15T19:54:16Z

On Fri, 15 Dec 2023 10:22:30 -0800 Rafael Silva ***@***.***> wrote: @koendv Got some time and rebased this on main. Unfortunately the last commit is extremely experimental and not in a state for a clean rebase, so I just reverted the files to the state on the original PR, meaning it reverts some probably important changes on the current main, beware! It should work for scan of CH32 Risc-V chips with the WCH-LinkE, I just tested.

OK. Appreciated. koen

dragonmux

Apparently we started a review and then failed to ever actually post it, so here we are - it's incomplete, but a start.

dragonmux · 2023-12-15T21:30:36Z

src/command.c

@@ -51,6 +51,7 @@ static bool cmd_help(target_s *t, int argc, const char **argv);

 static bool cmd_jtag_scan(target_s *target, int argc, const char **argv);
 static bool cmd_swd_scan(target_s *target, int argc, const char **argv);
+static bool cmd_rvswd_scan(target_s *target, int argc, const char **argv);


This should probably be defined contingent on ENABLE_RISCV and we'd suggest that, at least for now, this be limited to BMDA. Iff we can figure out how to implement the protocol in the firmware we can then de-restrict it by removing the suggested check for PC_HOSTED.

That makes sense, I will consider how to gate this when it's more complete, there will still be a native implementation

src/platforms/hosted/wchlink.c

dragonmux · 2023-12-17T08:03:42Z

src/platforms/hosted/wchlink.c

+				break;
+			}
+			bmda_probe_info.usb_link->interface = idx;
+			descriptor = interface_desc;


Is this not missing a break; after this assignment?

I believe this was copied from JLink, which also looks like it's missing a break, I refactored it here, but it's pending on testing still.

src/platforms/hosted/wchlink.c

mean00 · 2024-08-09T05:23:13Z

In case it is helpful to make things move forward , please find attached
a partially reverse engineered RVSWD/DM protocol document (jpeg image). it is incomplete but enough to make it work.

( as an example, there is a driver written in basic c++ here : https://github.com/mean00/swindle/blob/main/swindle/src/bmp_rvTap.cpp , it could be used as a starting point to write a native BMP driver. It is full of #define macros due to popular demand. It works with CH32V2 and CH32V3)

Thank you.

perigoso · 2024-11-07T15:37:49Z

Thank you very much @mean00, I'm planing on picking this up again soon, but it might take some time to get back up to speed

Used to mark codes that are not part of the JEP106 or any other standard but are used internally by BMD to identify targets that don't provide a usable identification codes

write_char writes a single char into a char buffer at the provided offset, returns the offset incremented by 1 Memory safety safeguards are in place, if no buffer is provided, a buffer size of 0 is given, or the offset is out of bounds of the buffer, the buffer is not accessed, but the offset is still incremented Target use case is using in special print functions behaving similar to snprintf

…ogbuf when sysbus and abstract memory access is not available

perigoso force-pushed the feature/wch-support branch 2 times, most recently from 177c4be to 095148d Compare February 23, 2023 16:04

dragonmux added the New Target New debug target label Feb 23, 2023

dragonmux added this to the v2.0 release milestone Feb 23, 2023

perigoso mentioned this pull request Feb 28, 2023

How is the flash programmed? openwch/ch32v003#3

Open

perigoso force-pushed the feature/wch-support branch from 095148d to d2969a1 Compare July 31, 2023 22:54

perigoso mentioned this pull request Aug 2, 2023

Feature/vid pid map wildcard #1585

Merged

6 tasks

perigoso force-pushed the feature/wch-support branch from d2969a1 to 259a359 Compare August 11, 2023 17:39

perigoso mentioned this pull request Aug 11, 2023

RISCV: Add some quirks to be compatible with CH32V3x chips #1576

Closed

1 task

perigoso force-pushed the feature/wch-support branch 2 times, most recently from 762c495 to f9232ca Compare August 11, 2023 21:46

perigoso force-pushed the feature/wch-support branch from f9232ca to 3df1a41 Compare August 22, 2023 00:13

perigoso mentioned this pull request Sep 1, 2023

Target flash algorithm optimizations #1569

Open

9 tasks

perigoso force-pushed the feature/wch-support branch from 3df1a41 to 7e548c9 Compare October 5, 2023 12:11

perigoso mentioned this pull request Oct 5, 2023

WIP: stm32 flash rework + ch32 flash rework and implementation #1642

Draft

6 tasks

perigoso force-pushed the feature/wch-support branch from 7e548c9 to 9ac6516 Compare October 5, 2023 15:36

perigoso force-pushed the feature/wch-support branch 3 times, most recently from 828ef60 to 820b35c Compare December 15, 2023 18:13

perigoso force-pushed the feature/wch-support branch from 820b35c to 0b08aec Compare January 12, 2024 19:42

dragonmux requested changes Jan 12, 2024

View reviewed changes

perigoso force-pushed the feature/wch-support branch 4 times, most recently from c94ceed to bbdc854 Compare January 17, 2024 15:07

perigoso added 13 commits November 25, 2024 16:10

hosted: barebones wch-link implementation

06af671

hosted/wchlink: implement DMI transfer

466049b

riscv_debug: expose DMI operation and status defines

de413af

jep106: add BMD internal flag

0e75dde

Used to mark codes that are not part of the JEP106 or any other standard but are used internally by BMD to identify targets that don't provide a usable identification codes

jep106: add internal WCH non-jep106 code

50ffc29

riscv_jtag_dtm: move RV_DMI_TOO_SOON handling one level up

117562f

hosted/wchlink: implement RISC-V DTM handler

03441a8

command: add rvswd scan routine command

ee4269f

hosted/wchlink: implement RVSWD scan

7c15658

riscv32: add ch32v3 target probe

6fa3a98

ch32vx: implement electronic signature (ESIG) register handling

488dfcc

riscv32: add ch32v003 target probe

2c08951

perigoso force-pushed the feature/wch-support branch from bbdc854 to 4dfef3c Compare November 25, 2024 16:10

perigoso added 7 commits November 25, 2024 16:24

riscv_debug: formally parse the ISA subset

ab51224

riscv_debug: use the ISA subset as the target core name

5b65fa6

riscv_debug: fix typo

b332e50

riscv64: fix typo

abd5766

riscv_debug: update RV_CSR macros

b81e1a5

!experimental! riscv32: add hacky fallback memory access using the pr…

0d3768b

…ogbuf when sysbus and abstract memory access is not available

rvswd: gate rvswd functionality behind platform define

1ce1332

perigoso force-pushed the feature/wch-support branch from 4dfef3c to 06e298d Compare November 25, 2024 16:24

experimental: start working towards a native implementation

2a30df5

perigoso force-pushed the feature/wch-support branch from 06e298d to 2a30df5 Compare November 25, 2024 16:30

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Feature: WCH RISC-V support #1399

Feature: WCH RISC-V support #1399

perigoso commented Feb 23, 2023 •

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mean00 commented Aug 9, 2024 •

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perigoso commented Nov 7, 2024

Feature: WCH RISC-V support #1399

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Feature: WCH RISC-V support #1399

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perigoso commented Feb 23, 2023 • edited Loading

Detailed description

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dragonmux commented Oct 31, 2023

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