clippy lint

breqdev · Apr 14, 2024 · 69ba92e · 69ba92e
1 parent 83adeb4
commit 69ba92e
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Showing 2 changed files with 20 additions and 22 deletions.
diff --git a/src/memory/mos652x/pia.rs b/src/memory/mos652x/pia.rs
@@ -68,7 +68,7 @@ impl PiaPortRegisters {
       // CX1
       if cx1 != prev_cx1 {
         let direction = self.control & pia_control_bits::C1_ACTIVE_TRANSITION;
-        if (direction == 0 && cx1 == false) || (direction != 0 && cx1 == true) {
+        if (direction == 0 && !cx1) || (direction != 0 && cx1) {
           // matching edge detected
           self.control |= pia_control_bits::C1_ACTIVE_TRANSITION_FLAG;
 
@@ -83,7 +83,7 @@ impl PiaPortRegisters {
         // input
         if cx2 != prev_cx2 {
           let direction = self.control & pia_control_bits::C2_INPUT_ACTIVE_TRANSITION;
-          if (direction == 0 && cx2 == false) || (direction != 0 && cx2 == true) {
+          if (direction == 0 && !cx2) || (direction != 0 && cx2) {
             // matching edge detected
             self.control |= pia_control_bits::C2_ACTIVE_TRANSITION_FLAG;
 

diff --git a/src/memory/mos652x/via.rs b/src/memory/mos652x/via.rs
@@ -213,17 +213,16 @@ impl Memory for Via {
       }
     }
 
-    if self.pcr & pcr_control_bits::CA2_DIRECTION != 0 {
-      if (self.pcr & pcr_control_bits::CA2_INPUT_ACTIVE_TRANSITION == 0
+    if (self.pcr & pcr_control_bits::CA2_DIRECTION != 0)
+      && (self.pcr & pcr_control_bits::CA2_INPUT_ACTIVE_TRANSITION == 0
         && ca2 == ActiveTransition::Rising)
-        || (self.pcr & pcr_control_bits::CA2_INPUT_ACTIVE_TRANSITION != 0
-          && ca2 == ActiveTransition::Falling)
-      {
-        self.interrupts.set_flag(interrupt_bits::CA2);
-
-        if self.interrupts.is_enabled(interrupt_bits::CA2) {
-          active_interrupt = ActiveInterrupt::IRQ;
-        }
+      || (self.pcr & pcr_control_bits::CA2_INPUT_ACTIVE_TRANSITION != 0
+        && ca2 == ActiveTransition::Falling)
+    {
+      self.interrupts.set_flag(interrupt_bits::CA2);
+
+      if self.interrupts.is_enabled(interrupt_bits::CA2) {
+        active_interrupt = ActiveInterrupt::IRQ;
       }
     }
 
@@ -238,17 +237,16 @@ impl Memory for Via {
       }
     }
 
-    if self.pcr & pcr_control_bits::CB2_DIRECTION != 0 {
-      if (self.pcr & pcr_control_bits::CB2_INPUT_ACTIVE_TRANSITION == 0
+    if (self.pcr & pcr_control_bits::CB2_DIRECTION != 0)
+      && (self.pcr & pcr_control_bits::CB2_INPUT_ACTIVE_TRANSITION == 0
         && cb2 == ActiveTransition::Rising)
-        || (self.pcr & pcr_control_bits::CB2_INPUT_ACTIVE_TRANSITION != 0
-          && cb2 == ActiveTransition::Falling)
-      {
-        self.interrupts.set_flag(interrupt_bits::CB2);
-
-        if self.interrupts.is_enabled(interrupt_bits::CB2) {
-          active_interrupt = ActiveInterrupt::IRQ;
-        }
+      || (self.pcr & pcr_control_bits::CB2_INPUT_ACTIVE_TRANSITION != 0
+        && cb2 == ActiveTransition::Falling)
+    {
+      self.interrupts.set_flag(interrupt_bits::CB2);
+
+      if self.interrupts.is_enabled(interrupt_bits::CB2) {
+        active_interrupt = ActiveInterrupt::IRQ;
       }
     }