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@rachitnigam rachitnigam released this 31 Aug 12:22
  • BREAKING: Deprecate Cell::find_with_attr in favor of Cell::find_with_unique_attr. The former is error-prone because pass logic might implicitly assume that there is only one port with a particular attribute.
  • BREAKING: Redesign the ir::Rewriter interface to take all the rewrite maps when constructing the ir::Rewriter struct.
  • Merge the logic of compile-ref pass into compile-invoke so that ref cells can be invoked.
  • The guard! macro supports parsing complex guard expressions that use logical connectives and comparison operators.
  • The calyx library no longer exposes any methods and should not be depended upon. Instead, the new calyx-backend crate provides the code needed to emit Verilog from Calyx.