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Agendas and summaries for Calyx meetings

March 26

• Graph coloring merger (#444)
• Two's complement fixed-point (#445)
• Recap the group timing fix (#446)

March 19

• Chris: Update on FP, FP representation, and other open PRs
• YooNa & Karen: Current state of interpreter + planning a demo
• Alex, Andrii: Demo implementation & next steps
• Griffin: Update + Next steps
• General state of issues and PR (let's start knocking them off!)

March 15

• Recap of fixed-point progress from Chris (#421)
• Griffin; Finding a new meeting time
• Welcoming & onboarding Andrii

Mar 8

• A real fixed point library and numeric system
  • The current library isn't that good and well tested
  • The FP operators are the same as the bitnum ones. No reason to keep them separate.
• Only if there's time: brief overview of modules thoughts (#419).

Mar 1

• welcome YoungSeok (?)
• Interpreter updates
• TVM
• go / done interface

Feb 22

• Interpreter design discussion.
• [Adrian] ADA demo.
• Exponentiation?
• Public-facing website update?

Feb 15

• Merging #292.
• Relay status and Dahlia frontend issues (if any)
• State of demo website.
  • For the future, maybe: setting up a "marketing" website, GitHub Discussions.

Feb 2

• Systolic array speedup mystery updates (postponed)
• Relay
  • Quantizing networks
  • Testing integration
• NTT
  • Add milestone for compiling NTT-256.
• Invoke ports

Jan 26

• Relay demo
• Merging https://github.com/cucapra/dahlia/pull/340
• NTT status/updates
• Brief outline for steps needed to get FuTIL running on FGPAs
• Systolic array speedup mystery updates (postponed)

Jan 19

• NTT implementation: Try parallelizing the programs by either unrolling the Dahlia loops or writing a butterfly transform generator in Calyx.
• Talked about pipelining operator and the need for interfaces that can catch when certain signals arrive.
  • Some notion of how long a signal needs to stay "alive" for (in number of cycles) seems important when doing this.
  • The interface should capture initiation intervals (II) for the pipeline
• Relay
  • Get VGG working to the point where the whole VGG program can be simulated on Verilator.