Integration at the University of Rome Tor Vergata

Updates made during integration tests from 14th - 16th June 2019 at the University of Rome Tor Vergata lab.

Changes since previous release:

• Fixed issue with not reading Zynq files from FTP server
• Added HV _PACKET readout into the main CPU run file
• Updated ArduinoManager -> AnalogManager to read out thermistors through new interface
• Changed HV ramp up to start at DAC 2500 / 700 V instead of 0 V
• Updated CamManager::KillCamAcq() to make program shutdown more robust
• Added automated boot scripts to main SW and tested
• Added ZynqManager::InstrumentClean() command to program flow (clears FTP server)
• Added command line option to set dynode voltage for individual EC units
• Fixed bug which stopped proper HVPS cathode setting
• Make AnalogManager::ProcessAnalogData() only write THERM_PACKETs during local night