Update src/test/scala/chiselTests/ModuleChoiceSpec.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
chipsalliance · Dec 10, 2024 · 8dbb9b8 · 8dbb9b8
1 parent 7a2a62f
commit 8dbb9b8
Showing 1 changed file with 5 additions and 4 deletions.
diff --git a/src/test/scala/chiselTests/ModuleChoiceSpec.scala b/src/test/scala/chiselTests/ModuleChoiceSpec.scala
@@ -141,10 +141,11 @@ class AddGroupSpec extends ChiselFlatSpec with Utils with MatchesAndOmits {
     val chirrtl = ChiselStage.emitCHIRRTL(new ModuleWithoutChoice, Array("--full-stacktrace"))
 
     info("CHIRRTL emission looks correct")
-    matchesAndOmits(chirrtl)(
-      "option Platform :",
-      "FPGA",
-      "ASIC"
+    fileCheckString(chirrtl)(
+      """|CHECK: option Platform :
+         |CHECK-NEXT: FPGA
+         |CHECK-NEXT: ASIC
+         |""".stripMargin
     )()
   }
 }