Merge pull request #4518 from chipsalliance/adkian-sifive/scala2-src-…

…compatibility-changes-for-scala3

[Scala3] Scala2 src compatibility changes for Scala3

src/main/scala/chisel3/ltl/LTL.scala → src/main/scala-2/chisel3/ltl/LTL.scala

@@ -5,7 +5,7 @@ package chisel3.ltl
 import chisel3._
 import chisel3.layer.{block, Layer}
 import chisel3.util.circt._
-import chisel3.experimental.hierarchy.{Instance, Instantiate}
+import chisel3.experimental.hierarchy.Instance
 import chisel3.experimental.SourceInfo
 
 /** An opaque sequence returned by an intrinsic.

src/main/scala/chisel3/simulator/package.scala → src/main/scala-2/chisel3/simulator/package.scala

@@ -5,6 +5,7 @@ import chisel3.reflect.DataMirror
 import chisel3.experimental.dataview.reifyIdentityView
 import scala.collection.mutable
 import java.nio.file.{Files, Path, Paths}
+import firrtl.seqToAnnoSeq
 
 package object simulator {
 

src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala

@@ -21,7 +21,7 @@ object scanLeftOr {
     }
 
     def helper(s: Int, x: UInt): UInt =
-      if (s >= width) x else helper(s + s, x | (x << s)(width - 1, 0))
+      if (s >= width) x else helper(s + s, x | (x << s).apply(width - 1, 0))
     helper(1, data)(width - 1, 0)
   }
 }

src/main/scala/chisel3/stage/ChiselAnnotations.scala

@@ -20,7 +20,7 @@ import chisel3.layer.Layer
 import chisel3.internal.{Builder, WarningFilter}
 import chisel3.internal.firrtl.ir.Circuit
 import chisel3.internal.firrtl.Converter
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.ir.{CircuitWithAnnos, Serializer}
 import scala.util.control.NonFatal
 import java.io.{BufferedWriter, File, FileWriter}

src/main/scala/chisel3/stage/package.scala

@@ -4,7 +4,7 @@ package chisel3
 
 import firrtl._
 import firrtl.options.OptionsView
-
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import chisel3.internal.firrtl.ir.{Circuit => ChiselCircuit}
 import chisel3.stage.CircuitSerializationAnnotation.FirrtlFileFormat
 

src/main/scala/chisel3/stage/phases/AddDedupGroupAnnotations.scala

@@ -1,6 +1,6 @@
 package chisel3.stage.phases
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase}
 import firrtl.options.Viewer.view
 import firrtl.transforms.DedupGroupAnnotation

src/main/scala/chisel3/stage/phases/AddImplicitOutputAnnotationFile.scala

@@ -3,7 +3,7 @@
 package chisel3.stage.phases
 
 import chisel3.stage.ChiselCircuitAnnotation
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, OutputAnnotationFileAnnotation, Phase}
 
 /** Adds an [[firrtl.options.OutputAnnotationFileAnnotation]] if one does not exist. This replicates old behavior where

src/main/scala/chisel3/stage/phases/AddImplicitOutputFile.scala

@@ -2,7 +2,7 @@
 
 package chisel3.stage.phases
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase}
 
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation}

src/main/scala/chisel3/stage/phases/AddSerializationAnnotations.scala

@@ -2,7 +2,7 @@
 
 package chisel3.stage.phases
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase}
 import firrtl.options.Viewer.view
 

src/main/scala/chisel3/stage/phases/Checks.scala

@@ -13,6 +13,7 @@ import firrtl.options.{Dependency, OptionsException, Phase}
   * `chisel3.stage.ChiselStage`.
   */
 class Checks extends Phase {
+  import firrtl.annoSeqToSeq
 
   override def prerequisites = Seq.empty
   override def optionalPrerequisites = Seq.empty

src/main/scala/chisel3/stage/phases/Convert.scala

@@ -4,7 +4,7 @@ package chisel3.stage.phases
 
 import chisel3.internal.firrtl.Converter
 import chisel3.stage.ChiselCircuitAnnotation
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase}
 import firrtl.stage.FirrtlCircuitAnnotation
 

src/main/scala/chisel3/stage/phases/Elaborate.scala

@@ -10,13 +10,14 @@ import chisel3.stage.{
   ChiselCircuitAnnotation,
   ChiselGeneratorAnnotation,
   ChiselOptions,
+  ChiselOptionsView,
   DesignAnnotation,
   ThrowOnFirstErrorAnnotation
 }
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase}
 import firrtl.options.Viewer.view
-import logger.LoggerOptions
+import logger.{LoggerOptions, LoggerOptionsView}
 
 import scala.collection.mutable.ArrayBuffer
 

src/main/scala/chisel3/stage/phases/Emitter.scala

@@ -2,11 +2,11 @@
 
 package chisel3.stage.phases
 
-import firrtl.AnnotationSeq
-import firrtl.options.{Dependency, Phase, StageOptions}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
+import firrtl.options.{Dependency, Phase, StageOptions, StageOptionsView}
 import firrtl.options.Viewer.view
 
-import chisel3.stage.{ChiselCircuitAnnotation, ChiselOptions, CircuitSerializationAnnotation}
+import chisel3.stage.{ChiselCircuitAnnotation, ChiselOptions, ChiselOptionsView, CircuitSerializationAnnotation}
 import CircuitSerializationAnnotation.FirrtlFileFormat
 
 import java.io.{BufferedOutputStream, File, FileOutputStream}

src/main/scala/chisel3/testers/TesterDriver.scala

@@ -5,7 +5,7 @@ package chisel3.testers
 import chisel3._
 import chisel3.stage.phases.{Convert, Elaborate, Emitter}
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation}
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.annotations.NoTargetAnnotation
 import firrtl.options.{Dependency, Phase, PhaseManager, TargetDirAnnotation, Unserializable}
 import firrtl.stage.FirrtlCircuitAnnotation

src/main/scala/chisel3/util/BitwiseImpl.scala

@@ -56,11 +56,13 @@ private[chisel3] trait ReverseImpl {
         var res = in
         var shift = length >> 1
         var mask = ((BigInt(1) << length) - 1).asUInt(length.W)
-        do {
+        var initial = true
+        while (initial || shift > 0) {
+          initial = false
           mask = mask ^ (mask(length - shift - 1, 0) << shift)
-          res = ((res >> shift) & mask) | ((res(length - shift - 1, 0) << shift) & ~mask)
+          res = ((res >> shift) & mask) | ((res(length - shift - 1, 0) << shift) & !mask)
           shift = shift >> 1
-        } while (shift > 0)
+        }
         res
       case _ =>
         val half = (1 << log2Ceil(length)) / 2

src/main/scala/chisel3/util/OneHot.scala

@@ -61,8 +61,8 @@ object UIntToOH {
     case 1 => 1.U(1.W)
     case _ =>
       val shiftAmountWidth = log2Ceil(width)
-      val shiftAmount = in.pad(shiftAmountWidth)(shiftAmountWidth - 1, 0)
-      (1.U << shiftAmount)(width - 1, 0)
+      val shiftAmount = in.pad(shiftAmountWidth).apply(shiftAmountWidth - 1, 0)
+      (1.U << shiftAmount).apply(width - 1, 0)
   }
 }
 

src/main/scala/chisel3/util/circt/DPI.scala

@@ -3,8 +3,7 @@
 package chisel3.util.circt.dpi
 
 import chisel3._
-
-import chisel3.experimental.{IntParam, IntrinsicModule, Param, StringParam}
+import chisel3.experimental.{fromIntToIntParam, fromStringToStringParam, IntParam, IntrinsicModule, Param, StringParam}
 
 private object GetDPIParams {
   def apply(

src/main/scala/chisel3/util/circt/PlusArgsTest.scala

@@ -3,6 +3,7 @@
 package chisel3.util.circt
 
 import chisel3._
+import chisel3.experimental.fromStringToStringParam
 import chisel3.internal.Builder
 
 object PlusArgsTest {

src/main/scala/chisel3/util/circt/PlusArgsValue.scala

@@ -5,8 +5,14 @@ package chisel3.util.circt
 import scala.language.reflectiveCalls
 
 import chisel3._
+import chisel3.experimental.fromStringToStringParam
 import chisel3.internal.Builder
 
+class PlusArgsRetBundle[T <: Data](gen: => T) extends Bundle {
+  val found = Output(Bool())
+  val result = Output(gen)
+}
+
 /** Create an intrinsic which generates a verilog \$value\$plusargs.  This returns a
   * value as indicated by the format string and a flag for whether the value
   * was found.
@@ -21,13 +27,9 @@ object PlusArgsValue {
     * b.value
     * }}}
     */
-  def apply[T <: Data](gen: T, str: String) = {
+  def apply[T <: Data](gen: T, str: String): PlusArgsRetBundle[T] = {
     val ty = if (gen.isSynthesizable) chiselTypeOf(gen) else gen
-    class PlusArgsRetBundle extends Bundle {
-      val found = Output(Bool())
-      val result = Output(ty)
-    }
-    IntrinsicExpr("circt_plusargs_value", new PlusArgsRetBundle, "FORMAT" -> str)()
+    IntrinsicExpr("circt_plusargs_value", new PlusArgsRetBundle(ty), "FORMAT" -> str)()
   }
 
   /** Creates an intrinsic which calls \$value\$plusargs and returns a default
@@ -38,7 +40,7 @@ object PlusArgsValue {
     * }}}
     */
   def apply[T <: Data](gen: T, str: String, default: T): T = {
-    val result = apply(gen, str)
+    val result: PlusArgsRetBundle[T] = apply(gen, str)
     Mux(result.found, result.result, default)
   }
 }

src/main/scala/chisel3/util/experimental/decode/decoder.scala

@@ -7,6 +7,7 @@ import chisel3.experimental.{annotate, requireIsAnnotatable, ChiselAnnotation}
 import chisel3.util.{pla, BitPat}
 import chisel3.util.experimental.{getAnnotations, BitSet}
 import firrtl.annotations.Annotation
+import firrtl.annoSeqToSeq
 import logger.LazyLogging
 
 object decoder extends LazyLogging {

src/main/scala/chisel3/util/experimental/getAnnotations.scala

@@ -1,7 +1,7 @@
 package chisel3.util.experimental
 
 import chisel3.internal.Builder
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 
 object getAnnotations {
 

src/main/scala/chisel3/verilog.scala

@@ -2,7 +2,7 @@ package chisel3
 
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage.{CIRCTTarget, CIRCTTargetAnnotation, ChiselStage}
-import firrtl.{AnnotationSeq, EmittedVerilogCircuitAnnotation}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq, EmittedVerilogCircuitAnnotation}
 import firrtl.options.{Dependency, PhaseManager}
 
 object getVerilogString {

src/main/scala/circt/stage/Annotations.scala

@@ -2,7 +2,7 @@
 
 package circt.stage
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.annotations.{Annotation, NoTargetAnnotation}
 import firrtl.options.{CustomFileEmission, HasShellOptions, OptionsException, ShellOption, Unserializable}
 import firrtl.options.Viewer.view

src/main/scala/circt/stage/ChiselStage.scala

@@ -5,7 +5,7 @@ package circt.stage
 import chisel3.RawModule
 import chisel3.stage.{ChiselCircuitAnnotation, ChiselGeneratorAnnotation, CircuitSerializationAnnotation}
 import chisel3.stage.CircuitSerializationAnnotation.FirrtlFileFormat
-import firrtl.{AnnotationSeq, EmittedVerilogCircuitAnnotation}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq, EmittedVerilogCircuitAnnotation}
 import firrtl.options.{CustomFileEmission, Dependency, Phase, PhaseManager, Stage, StageMain, Unserializable}
 import firrtl.stage.FirrtlCircuitAnnotation
 import logger.LogLevelAnnotation

src/main/scala/circt/stage/Shell.scala

@@ -20,7 +20,7 @@ import firrtl.options.BareShell
 import firrtl.options.TargetDirAnnotation
 import logger.{ClassLogLevelAnnotation, LogClassNamesAnnotation, LogFileAnnotation, LogLevelAnnotation}
 
-trait CLI { this: BareShell =>
+trait CLI extends BareShell { this: BareShell =>
 
   /** Include options for logging
     *

src/main/scala/circt/stage/package.scala

@@ -4,7 +4,7 @@ package circt
 
 import circt.stage.{CIRCTOption, CIRCTTargetAnnotation, PreserveAggregate}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, AnnotationSeq}
 import firrtl.options.OptionsView
 import firrtl.stage.{FirrtlOption, OutputFileAnnotation}
 

src/main/scala/circt/stage/phases/AddImplicitOutputFile.scala

@@ -4,9 +4,9 @@ package circt.stage.phases
 
 import circt.stage.SplitVerilog
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq}
 import firrtl.options.{Dependency, Phase, Viewer}
-import firrtl.stage.{FirrtlOptions, OutputFileAnnotation}
+import firrtl.stage.{FirrtlOptions, FirrtlOptionsView, OutputFileAnnotation}
 
 /** [[firrtl.options.Phase Phase]] that adds an [[firrtl.stage.OutputFileAnnotation OutputFileAnnotation]] if one does
   * not already exist.

src/main/scala/circt/stage/phases/CIRCT.scala

@@ -7,19 +7,28 @@ import chisel3.BuildInfo.{firtoolVersion, version => chiselVersion}
 import chisel3.InternalErrorException
 import chisel3.experimental.hierarchy.core.ImportDefinitionAnnotation
 import chisel3.stage.{ChiselCircuitAnnotation, DesignAnnotation, SourceRootAnnotation}
-import circt.stage.{CIRCTOptions, CIRCTTarget, EmittedMLIR, PreserveAggregate}
+import circt.stage.{CIRCTOptions, CIRCTOptionsView, CIRCTTarget, EmittedMLIR, PreserveAggregate}
 import firrtl.annotations.JsonProtocol
 import firrtl.ir.CircuitWithAnnos
 import firrtl.options.Viewer.view
-import firrtl.options.{CustomFileEmission, Dependency, OptionsException, Phase, StageOptions, Unserializable}
-import firrtl.stage.FirrtlOptions
-import firrtl.{AnnotationSeq, EmittedVerilogCircuit, EmittedVerilogCircuitAnnotation}
+import firrtl.options.{
+  CustomFileEmission,
+  Dependency,
+  OptionsException,
+  Phase,
+  StageOptions,
+  StageOptionsView,
+  Unserializable
+}
+import firrtl.stage.{FirrtlOptions, FirrtlOptionsView}
+import firrtl.{annoSeqToSeq, seqToAnnoSeq, AnnotationSeq, EmittedVerilogCircuit, EmittedVerilogCircuitAnnotation}
 
 import java.io.File
 import scala.collection.mutable
 import scala.util.control.NoStackTrace
 import firrtl.EmittedBtor2CircuitAnnotation
 import firrtl.EmittedBtor2Circuit
+import org.json4s.convertToJsonInput
 
 private object Helpers {
   implicit class LogLevelHelpers(logLevel: LogLevel.Value) {

src/main/scala/circt/stage/phases/Checks.scala

@@ -4,7 +4,7 @@ package circt.stage.phases
 
 import circt.stage.{CIRCTTargetAnnotation, SplitVerilog}
 
-import firrtl.AnnotationSeq
+import firrtl.{annoSeqToSeq, AnnotationSeq}
 import firrtl.annotations.Annotation
 import firrtl.options.{Dependency, OptionsException, Phase, TargetDirAnnotation}
 import firrtl.stage.OutputFileAnnotation