Add input seq length check to Mux1H and PriorityMux

Added a new require to check that the input sequences have the same
length in both Mux1H and PriorityMux implementations.

src/main/scala/chisel3/util/MuxImpl.scala

@@ -23,8 +23,10 @@ import chisel3.experimental.SourceInfo
   * @note results unspecified unless exactly one select signal is high
   */
 object Mux1H {
-  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T =
+  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = {
+    require(sel.size == in.size, "Mux1H: Number of select signals and inputs must match")
     apply(sel.zip(in))
+  }
   def apply[T <: Data](in:  Iterable[(Bool, T)]): T = SeqUtils.oneHotMux(in)
   def apply[T <: Data](sel: UInt, in: Seq[T]): T =
     apply((0 until in.size).map(sel(_)), in)
@@ -46,7 +48,10 @@ object Mux1H {
   */
 object PriorityMux {
   def apply[T <: Data](in:  Seq[(Bool, T)]): T = SeqUtils.priorityMux(in)
-  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = apply(sel.zip(in))
+  def apply[T <: Data](sel: Seq[Bool], in: Seq[T]): T = {
+    require(sel.size == in.size, "PriorityMux: Number of select signals and inputs must match")
+    apply(sel.zip(in))
+  }
   def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
 }
 

src/test/scala/chiselTests/OneHotMuxSpec.scala

@@ -31,6 +31,12 @@ class OneHotMuxSpec extends AnyFreeSpec with Matchers with ChiselRunners {
     }
     e.getMessage should include("Mux1H must have a non-empty argument")
   }
+  "Mux1H should give a error when given two different size" in {
+    val e = intercept[IllegalArgumentException] {
+      Mux1H(Seq(true.B, true.B), Seq(1.U, 2.U, 3.U))
+    }
+    e.getMessage should include("Mux1H: Number of select signals and inputs must match")
+  }
 
 }
 

src/test/scala/chiselTests/util/PriorityMuxSpec.scala

@@ -47,6 +47,13 @@ class PriorityMuxSpec extends ChiselFlatSpec {
     assertTesterPasses(new PriorityMuxTester)
   }
 
+  it should "give a error when inputs are two different size" in {
+    val e = intercept[IllegalArgumentException] {
+      PriorityMux(Seq(true.B, true.B), Seq(1.U, 2.U, 3.U))
+    }
+    e.getMessage should include("PriorityMux: Number of select signals and inputs must match")
+  }
+
   it should "be stack safe" in {
     emitCHIRRTL(new RawModule {
       val n = 1 << 15