Skip to content

Chisel v3.6.0-M2

Pre-release
Pre-release
Compare
Choose a tag to compare
@jackkoenig jackkoenig released this 09 Jan 18:55
v3.6.0-M2
62eec3c

Note: These release notes are a work-in-progress

The primary change in Chisel v3.6.0 is the transition from the Scala FIRRTL Compiler to the new MLIR FIRRTL Compiler. This will have a minimal impact on typical Chisel user APIs but a large impact on custom compiler flows. For more information, please see the ROADMAP.

Try it out using this Scastie!

Highlights

  • New implementation of the FIRRTL compiler
    • The FIRRTL compiler has been rewritten using MLIR.
    • Faster, better SystemVerilog emission, and a growing open-source community.
    • See CIRCT.
  • Refined connection semantics (#2806)
  • Paths in source locators (#2791)
    • Source locators now include a distinguishing path from the root of your workspace.
    • This enables errors that point to your specific line of Chisel from MFC.

Deprecations

Note that many more deprecations are coming before the release of 3.6.0.

  • Compatibility mode (import Chisel._)
  • The Scala FIRRTL Compiler
  • FixedPoint and related APIs
  • Intervals and related APIs

Removals

Many APIs deprecated in Chisel 3.5 have been removed in Chisel 3.6.
This includes (but is not limited to):

  • MultiIOModule (use Module)
  • Parenthesized forms of zero-arity methods (eg. .asUInt() is removed, use .asUInt)
  • RawModule.getPorts and chisel3.getModulePorts
  • stop with non-zero return code

Performance Improvements

While there have been many performance improvements included in the Chisel 3.5 release line, there are some new improvements that only apply to 3.6. Preliminary results show a speedup of 11% and 8% reduction in heap use. These results are sensitive to particular user designs so actual results may vary.

  • Optimize internal _ids datastructure to reduce its size: #2866
  • Avoid creating unnecessary clones: #2611
    • eg. IO(Input(UInt(8.W))) will now create only a single UInt object instead of 3
  • Removed reflective naming which removes an iteration of all Data within a Module: #2562
  • Removed TransitNames and thus 2 vars from every HasId: #2604

Other Changes

  • SystemVerilog Parameters for BlackBoxes are now emitted in alphabetical order

Migration

3.6.0-M2 includes everything from 3.5.5 and before. Some features are newly deprecated in 3.5.5 that are removed in 3.6.0-M2. Please bump to 3.5.5 before attempting to upgrade to 3.6.0-M2.

Additional Changes since 3.6.0-M1

  • Bump CIRCT support (originally chisel-circt) from 0.5.0 to 0.8.0 (#2878)
  • Fix string interpolation in util.exprimental.decode.bitset (#2882)
  • Bugfix waiveEach not casting. Add waiveAllAs (#2894)
  • [circt] Cleanup CIRCT error behavior (#2896, #2892)
  • Take into account opaque members in squeeze functions (#2904)
  • Clarify mismatched width error message (#2917)
  • Fix bug where Flipped did not properly flip (#2919)
  • Fix lazy cloning (#2921)

For complete changes since 3.6.0-M1, run

git log --oneline $(git merge-base origin/master v3.6.0-M1)..$(git merge-base origin/master v3.6.0-M2)
Assets 2
Loading