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Chisel v5.1.0
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@jackkoenig jackkoenig released this 16 Nov 06:36
· 55 commits to 5.x since this release
v5.1.0
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Features

  • Fix color emission to check for interactive terminal (backport #3334) (by @mergify[bot] in #3336)
    • Chisel will now detect when it should print warnings, errors, and deprecations in color.
    • Color can be controlled with environment variable CHISEL_USE_COLOR. Set to true to force Chisel to use color and false to disable it.
    • Due to how the JVM works, detection requires interactive stdout, stderr, and stdin. Build tools like SBT virtualize stdin and thus color will be disabled by default when running a Chisel main with SBT. Detection also requires environment variable TERM to be set to something other than dumb.
  • Add support for Instantiate for BlackBox, ExtModule, and IntrinsicModule (backport #3349) (by @mergify[bot] in #3351)
  • Add support for zero-width bit extraction (backport #3352) (by @mergify[bot] in #3354)
  • Implement a SyncReadMem wrapper with explicit read, write, and read/write ports (backport #3228) (by @mergify[bot] in #3362)
    This SyncReadMem wrapper is instantiated using a new object, SRAM.apply, and invokes .write, .read, and .readWrite to generate a desired number of read, write, and read/write ports. This function returns a new Bundle wire containing the control signals for each requested port.
  • SRAM API: Add a parameter to initialize the memory (backport #3364) (by @mergify[bot] in #3380)
    SRAM.apply and SRAM.masked now take a contents parameter, by default a None, which is a string path to a binary file on the filesystem which the SRAM should be initialized with.
  • Support literals and DontCare in DataView targets (backport #3389) (by @mergify[bot] in #3391)
  • SRAM API: Add multiple-clocked port API (backport #3383) (by @mergify[bot] in #3405)
    Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.
  • Add support for configurable warnings (backport #3414) (by @mergify[bot] in #3431)
    Add support for configurable warnings, see https://www.chisel-lang.org/chisel3/docs/explanations/warnings.html
  • Enrich ShiftRegister with SyncReadMem-based implementation. (backport #2891) (by @mergify[bot] in #3571)
    Supplement ShiftRegister with SyncReadMem-based implementation.
  • Add --dump-fir option to ChiselStage (backport #3453) (by @mergify[bot] in #3456)
    This option will dump the .fir before invoking firtool.
    • Additional changes:
      • Use os.lib for invoking firtool
      • Use lazy serialization to avoid holding the entire FIRRTL in memory.
      • Mix NoStackTrace into FirtoolNotFound
      • Fix detection of no firtool

API Deprecation

  • Deprecate calling .viewAs on non-hardware (backport #3395) (by @mergify[bot] in #3400)
    Also fix a crash that could occur when viewing a non-Data containing non-hardware Data.

Performance

  • Convert Vec dynamic index with a literal to static index (backport #3314) (by @mergify[bot] in #3319)
  • Fix issue where reify would do the same lookup twice (backport #3392) (by @mergify[bot] in #3397)
  • Optimize source locator escaping when emitting FIRRTL (backport #3439) (by @mergify[bot] in #3449)
    Only escape/unescape source locators that need it, avoids a String copy in the common case.

Fixes

  • Gate sys/personality.h include under define (backport #3307) (by @mergify[bot] in #3308)
  • Don't emit implicit clock warnings for SyncReadMem.readWrite when explicit clocks are used (backport #3313) (by @mergify[bot] in #3316)
  • Make svsim shutdown gracefully when the test throws an exception (backport #3309) (by @mergify[bot] in #3310)
    • Fixed an issue where throwing an assert from an svsim simulation run may kill the simulated process before it can finish writing a waveform.
  • Report Builder errors even when exception is thrown (backport #3341) (by @mergify[bot] in #3343)
    Chisel will to report multiple errors, but this can be cut short by any thrown Exception which would then take precedence over the previously encountered errors. Now Chisel will prioritize reporting errors even if an Exception is thrown.
  • Add messages to require statements in Math (backport #3385) (by @mergify[bot] in #3388)
    • log2 functions
    • unsignedBitLength
  • [svsim] Don't redirect simulation stderr to a pipe (backport #3403) (by @mergify[bot] in #3406)
    • Fixes an issue where simulations that logged to stderr could hang
  • Sanitize Record._elements (backport #3419) (by @mergify[bot] in #3427)
    Fixes a bug in D/I where unsanitary names would lead to a crash. It also makes the Printable output for Bundles and Records use the sanitary names which makes them better match the FIRRTL.
  • Restore BundleUpcastable (backport #3487) (by @mergify[bot] in #3494)
    Restore BundleUpcastable and deprecate it.
  • Fix DataMirror.internal.chiselTypeClone to preserve Scala type (backport #3553) (by @mergify[bot] in #3555)
  • Fix Decodetable (backport #3563) (by @mergify[bot] in #3580)
  • Add type ascription to implicits from instantiable (backport #3615) (by @mergify[bot] in #3618)
    This fixes Scala compiler warnings in Scala 2.13.12 requiring type ascriptions on public implicit definitions.

Documentation

  • Remove references to interval types from the website docs (backport #3345) (by @mergify[bot] in #3348)
    Fixes #3325
  • Bring ToC and Menu into alignment, some minor cleanup within docs (backport #3346) (by @mergify[bot] in #3347)
    Fix #3322
  • Changed Array to Seq in MuxLookup explantation (backport #3547) (by @mergify[bot] in #3550)

Dependency Updates

Build and Internal Changes

Full Changelog: v5.0.0...v5.1.0

Contributors

mergify and chiselbot
Assets 4
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