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19 Open 11 Closed
19 Open 11 Closed
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Issues list

VPR generates warnings about missing timing in testarch
#166 opened Feb 28, 2024 by sh-mcu8apps
AttributeError when converts IF to json
#162 opened Jun 28, 2022 by zhilix
FASM generators: add LUTRAM support for xc7
#128 opened Oct 1, 2021 by acomodi
Issues trying to create YAML device file from example
#117 opened Aug 5, 2021 by clavin-xlnx
4
XDC constraints attributes on cells/ports missing from the netlists
#109 opened Jul 12, 2021 by acomodi
1
Add support to emit VTR XML architecture file
#101 opened Jun 16, 2021 by acomodi
Allow patching of lists
#82 opened May 10, 2021 by gatecat
Allow patching of StringIdx values enhancement New feature or request
#81 opened May 10, 2021 by gatecat
Add FASM generator testing
#79 opened Apr 30, 2021 by acomodi
Cleaner nextpnr BBA generation enhancement New feature or request
#66 opened Apr 23, 2021 by gatecat
2
Invalid DCP when the BUFG route-thru is used
#61 opened Apr 12, 2021 by acomodi
Replace local license checks with the SymbiFlow/actions/checks@main action
#59 opened Apr 11, 2021 by mithro
1
Setup automatic publishing packages to PyPI
#35 opened Mar 18, 2021 by mithro
@mithro
2
Requiring a NULL tile at (0, 0) is Xilinx-specific
#34 opened Mar 17, 2021 by gatecat
5
Optimize node and pip walking
#31 opened Mar 2, 2021 by litghost
Improve YAML anchor names enhancement New feature or request
#30 opened Feb 25, 2021 by litghost
Add XML support to plaintext FPGA interchange
#29 opened Feb 25, 2021 by litghost
Remove rapidyaml git+https in requirements once rapidyaml is in PyPi
#11 opened Jan 28, 2021 by litghost
Need canonical storage solution to ensure binary consistency
#8 opened Jan 21, 2021 by litghost
2
ProTip! no:milestone will show everything without a milestone.