Single-Cycle-MIPS32

Checklists

• Design a synthesizable microprocessor MIPS32 in VHDL and implement it with single-cycle architecture.
• Translate block diagrams into RTL codes.
• Create design was functionally and behaviorally simulated in Quartus, Modelsim, and Vivado.

ALERT

Should you intend to use all the RTL codes, please do not forget to cite the author as:

-- This project was originally created by Christian Reivan, Bandung Institute of Technology.   
-- Created on 11/25/2021.   
-- I, hereby, declare that this RTL code is not used for any illegal or prohibited use.